38 lines
1.1 KiB
C
38 lines
1.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2025 MIPS.
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*/
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#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H
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#define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H
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#include <linux/types.h>
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#define RISCV_ISA_VENDOR_EXT_XMIPSEXECTL 0
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#ifndef __ASSEMBLER__
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struct riscv_isa_vendor_ext_data_list;
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extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips;
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#endif
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/* Extension specific instructions */
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/*
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* All of the xmipsexectl extension instructions are
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* ‘hint’ encodings of the SLLI instruction,
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* with rd = 0, rs1 = 0 and imm = 1 for IHB, imm = 3 for EHB,
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* and imm = 5 for PAUSE.
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* MIPS.PAUSE is an alternative opcode which is implemented to have the
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* same behavior as PAUSE on some MIPS RISCV cores.
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* MIPS.EHB clears all execution hazards before allowing
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* any subsequent instructions to execute.
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* MIPS.IHB clears all instruction hazards before
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* allowing any subsequent instructions to fetch.
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*/
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#define MIPS_PAUSE ASM_INSN_I("0x00501013\n\t")
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#define MIPS_EHB ASM_INSN_I("0x00301013\n\t")
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#define MIPS_IHB ASM_INSN_I("0x00101013\n\t")
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#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H
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