65 lines
2.7 KiB
C
65 lines
2.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8365_MMSYS_H
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#define __SOC_MEDIATEK_MT8365_MMSYS_H
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#define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0xf3c
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#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL 0xf4c
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#define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN 0xf50
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#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN 0xf54
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#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN 0xf60
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#define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0xf64
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#define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf68
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#define MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL 0xfd0
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#define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0xfd8
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#define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00 0xfdc
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#define MT8365_DISP_MS_IN_OUT_MASK GENMASK(3, 0)
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#define MT8365_RDMA0_SOUT_COLOR0 0x1
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#define MT8365_DITHER_MOUT_EN_DSI0 BIT(0)
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#define MT8365_DSI0_SEL_IN_DITHER 0x1
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#define MT8365_RDMA0_SEL_IN_OVL0 0x0
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#define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0
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#define MT8365_DISP_COLOR_SEL_IN_COLOR0 0x0
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#define MT8365_OVL0_MOUT_PATH0_SEL BIT(0)
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#define MT8365_RDMA1_SOUT_DPI0 0x1
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#define MT8365_DPI0_SEL_IN_RDMA1 0x0
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#define MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK 0x1
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#define MT8365_DPI0_SEL_IN_RDMA1 0x0
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static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
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MMSYS_ROUTE(OVL0, RDMA0,
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MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
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MT8365_DISP_MS_IN_OUT_MASK, MT8365_OVL0_MOUT_PATH0_SEL),
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MMSYS_ROUTE(OVL0, RDMA0,
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MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
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MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SEL_IN_OVL0),
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MMSYS_ROUTE(RDMA0, COLOR0,
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MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
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MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SOUT_COLOR0),
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MMSYS_ROUTE(COLOR0, CCORR,
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MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
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MT8365_DISP_MS_IN_OUT_MASK, MT8365_DISP_COLOR_SEL_IN_COLOR0),
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MMSYS_ROUTE(DITHER0, DSI0,
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MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
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MT8365_DISP_MS_IN_OUT_MASK, MT8365_DITHER_MOUT_EN_DSI0),
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MMSYS_ROUTE(DITHER0, DSI0,
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MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
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MT8365_DISP_MS_IN_OUT_MASK, MT8365_DSI0_SEL_IN_DITHER),
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MMSYS_ROUTE(RDMA0, COLOR0,
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MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
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MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0),
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MMSYS_ROUTE(RDMA1, DPI0,
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MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
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MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK,
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MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK),
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MMSYS_ROUTE(RDMA1, DPI0,
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MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
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MT8365_DISP_MS_IN_OUT_MASK, MT8365_DPI0_SEL_IN_RDMA1),
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MMSYS_ROUTE(RDMA1, DPI0,
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MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
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MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA1_SOUT_DPI0),
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};
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#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */
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