99 lines
2.8 KiB
YAML
99 lines
2.8 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller on GLYMUR
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maintainers:
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- Taniya Das <taniya.das@oss.qualcomm.com>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains for the MDSS instances on GLYMUR SoC.
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See also:
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include/dt-bindings/clock/qcom,dispcc-glymur.h
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properties:
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compatible:
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enum:
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- qcom,glymur-dispcc
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clocks:
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items:
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- description: Board CXO clock
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- description: Board sleep clock
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- description: DisplayPort 0 link clock
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- description: DisplayPort 0 VCO div clock
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- description: DisplayPort 1 link clock
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- description: DisplayPort 1 VCO div clock
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- description: DisplayPort 2 link clock
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- description: DisplayPort 2 VCO div clock
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- description: DisplayPort 3 link clock
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- description: DisplayPort 3 VCO div clock
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- description: DSI 0 PLL byte clock
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- description: DSI 0 PLL DSI clock
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- description: DSI 1 PLL byte clock
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- description: DSI 1 PLL DSI clock
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- description: Standalone PHY 0 PLL link clock
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- description: Standalone PHY 0 VCO div clock
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- description: Standalone PHY 1 PLL link clock
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- description: Standalone PHY 1 VCO div clock
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power-domains:
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description:
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A phandle and PM domain specifier for the MMCX power domain.
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maxItems: 1
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required-opps:
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description:
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A phandle to an OPP node describing required MMCX performance point.
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maxItems: 1
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required:
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- compatible
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- clocks
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- power-domains
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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clock-controller@af00000 {
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compatible = "qcom,glymur-dispcc";
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reg = <0x0af00000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>,
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<&mdss_dp_phy0 0>,
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<&mdss_dp_phy0 1>,
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<&mdss_dp_phy1 0>,
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<&mdss_dp_phy1 1>,
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<&mdss_dp_phy2 0>,
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<&mdss_dp_phy2 1>,
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<&mdss_dp_phy3 0>,
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<&mdss_dp_phy3 1>,
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<&mdss_dsi0_phy 0>,
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<&mdss_dsi0_phy 1>,
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<&mdss_dsi1_phy 0>,
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<&mdss_dsi1_phy 1>,
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<&mdss_phy0_link 0>,
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<&mdss_phy0_vco_div 0>,
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<&mdss_phy1_link 1>,
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<&mdss_phy1_vco_div 1>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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