83 lines
2.2 KiB
YAML
83 lines
2.2 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/cpufreq/mediatek,mt8196-cpufreq-hw.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Hybrid CPUFreq for MT8196/MT6991 series SoCs
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maintainers:
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- Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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description:
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MT8196 uses CPUFreq management hardware that supports dynamic voltage
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frequency scaling (dvfs), and can support several performance domains.
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properties:
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compatible:
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const: mediatek,mt8196-cpufreq-hw
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reg:
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items:
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- description: FDVFS control register region
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- description: OPP tables and control for performance domain 0
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- description: OPP tables and control for performance domain 1
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- description: OPP tables and control for performance domain 2
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"#performance-domain-cells":
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const: 1
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required:
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- compatible
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- reg
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- "#performance-domain-cells"
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additionalProperties: false
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examples:
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- |
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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performance-domains = <&performance 0>;
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reg = <0x000>;
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};
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/* ... */
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cpu6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-x4";
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enable-method = "psci";
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performance-domains = <&performance 1>;
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reg = <0x600>;
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};
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cpu7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-x925";
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enable-method = "psci";
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performance-domains = <&performance 2>;
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reg = <0x700>;
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};
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};
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/* ... */
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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performance: performance-controller@c2c2034 {
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compatible = "mediatek,mt8196-cpufreq-hw";
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reg = <0 0xc220400 0 0x20>, <0 0xc2c0f20 0 0x120>,
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<0 0xc2c1040 0 0x120>, <0 0xc2c1160 0 0x120>;
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#performance-domain-cells = <1>;
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};
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};
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