79 lines
1.7 KiB
YAML
79 lines
1.7 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Generic Interrupt Controller, version 5 Interrupt Wire Bridge (IWB)
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maintainers:
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- Lorenzo Pieralisi <lpieralisi@kernel.org>
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- Marc Zyngier <maz@kernel.org>
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description: |
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The GICv5 architecture defines the guidelines to implement GICv5
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compliant interrupt controllers for AArch64 systems.
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The GICv5 specification can be found at
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https://developer.arm.com/documentation/aes0070
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GICv5 has zero or more Interrupt Wire Bridges (IWB) that are responsible
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for translating wire signals into interrupt messages to the GICv5 ITS.
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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properties:
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compatible:
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const: arm,gic-v5-iwb
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reg:
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items:
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- description: IWB control frame
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"#address-cells":
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const: 0
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"#interrupt-cells":
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description: |
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The 1st cell corresponds to the IWB wire.
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The 2nd cell is the flags, encoded as follows:
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bits[3:0] trigger type and level flags.
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1 = low-to-high edge triggered
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2 = high-to-low edge triggered
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4 = active high level-sensitive
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8 = active low level-sensitive
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const: 2
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interrupt-controller: true
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msi-parent:
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maxItems: 1
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required:
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- compatible
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- reg
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- "#interrupt-cells"
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- interrupt-controller
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- msi-parent
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additionalProperties: false
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examples:
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- |
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interrupt-controller@2f000000 {
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compatible = "arm,gic-v5-iwb";
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reg = <0x2f000000 0x10000>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupt-controller;
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msi-parent = <&its0 64>;
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};
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...
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