83 lines
2.1 KiB
YAML
83 lines
2.1 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/xlnx,intc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx Interrupt Controller
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maintainers:
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- Michal Simek <michal.simek@amd.com>
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description:
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The controller is a soft IP core that is configured at build time for the
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number of interrupts and the type of each interrupt. These details cannot
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be changed at run time.
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properties:
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compatible:
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const: xlnx,xps-intc-1.00.a
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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"#interrupt-cells":
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const: 2
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description:
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Specifies the number of cells needed to encode an interrupt source.
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The value shall be a minimum of 1. The Xilinx device trees typically
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use 2 but the 2nd value is not used.
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interrupt-controller: true
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interrupts:
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maxItems: 1
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description:
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Specifies the interrupt of the parent controller from which it is chained.
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xlnx,kind-of-intr:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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A 32 bit value specifying the interrupt type for each possible interrupt
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(1 = edge, 0 = level). The interrupt type typically comes in thru
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the device tree node of the interrupt generating device, but in this case
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the interrupt type is determined by the interrupt controller based on how
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it was implemented.
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xlnx,num-intr-inputs:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 32
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description:
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Specifies the number of interrupts supported by the specific
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implementation of the controller.
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required:
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- reg
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- "#interrupt-cells"
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- interrupt-controller
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- xlnx,kind-of-intr
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- xlnx,num-intr-inputs
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additionalProperties: false
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examples:
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- |
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interrupt-controller@41800000 {
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compatible = "xlnx,xps-intc-1.00.a";
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reg = <0x41800000 0x10000>;
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#interrupt-cells = <2>;
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interrupt-controller;
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xlnx,kind-of-intr = <0x1>;
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xlnx,num-intr-inputs = <1>;
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};
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