183 lines
7.1 KiB
ReStructuredText
183 lines
7.1 KiB
ReStructuredText
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.. SPDX-License-Identifier: GPL-2.0
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.. include:: <isonum.txt>
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=======================================
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Compute Express Link: Linux Conventions
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=======================================
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There exists shipping platforms that bend or break CXL specification
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expectations. Record the details and the rationale for those deviations.
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Borrow the ACPI Code First template format to capture the assumptions
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and tradeoffs such that multiple platform implementations can follow the
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same convention.
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<(template) Title>
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==================
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Document
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--------
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CXL Revision <rev>, Version <ver>
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License
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-------
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SPDX-License Identifier: CC-BY-4.0
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Creator/Contributors
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--------------------
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Summary of the Change
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---------------------
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<Detail the conflict with the specification and where available the
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assumptions and tradeoffs taken by the hardware platform.>
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Benefits of the Change
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----------------------
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<Detail what happens if platforms and Linux do not adopt this
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convention.>
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References
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----------
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Detailed Description of the Change
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----------------------------------
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<Propose spec language that corrects the conflict.>
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Resolve conflict between CFMWS, Platform Memory Holes, and Endpoint Decoders
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============================================================================
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Document
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--------
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CXL Revision 3.2, Version 1.0
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License
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-------
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SPDX-License Identifier: CC-BY-4.0
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Creator/Contributors
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--------------------
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- Fabio M. De Francesco, Intel
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- Dan J. Williams, Intel
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- Mahesh Natu, Intel
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Summary of the Change
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---------------------
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According to the current Compute Express Link (CXL) Specifications (Revision
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3.2, Version 1.0), the CXL Fixed Memory Window Structure (CFMWS) describes zero
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or more Host Physical Address (HPA) windows associated with each CXL Host
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Bridge. Each window represents a contiguous HPA range that may be interleaved
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across one or more targets, including CXL Host Bridges. Each window has a set
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of restrictions that govern its usage. It is the Operating System-directed
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configuration and Power Management (OSPM) responsibility to utilize each window
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for the specified use.
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Table 9-22 of the current CXL Specifications states that the Window Size field
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contains the total number of consecutive bytes of HPA this window describes.
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This value must be a multiple of the Number of Interleave Ways (NIW) * 256 MB.
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Platform Firmware (BIOS) might reserve physical addresses below 4 GB where a
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memory gap such as the Low Memory Hole for PCIe MMIO may exist. In such cases,
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the CFMWS Range Size may not adhere to the NIW * 256 MB rule.
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The HPA represents the actual physical memory address space that the CXL devices
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can decode and respond to, while the System Physical Address (SPA), a related
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but distinct concept, represents the system-visible address space that users can
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direct transaction to and so it excludes reserved regions.
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BIOS publishes CFMWS to communicate the active SPA ranges that, on platforms
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with LMH's, map to a strict subset of the HPA. The SPA range trims out the hole,
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resulting in lost capacity in the Endpoints with no SPA to map to that part of
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the HPA range that intersects the hole.
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E.g, an x86 platform with two CFMWS and an LMH starting at 2 GB:
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+--------+------------+-------------------+------------------+-------------------+------+
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| Window | CFMWS Base | CFMWS Size | HDM Decoder Base | HDM Decoder Size | Ways |
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+========+============+===================+==================+===================+======+
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| 0 | 0 GB | 2 GB | 0 GB | 3 GB | 12 |
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+--------+------------+-------------------+------------------+-------------------+------+
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| 1 | 4 GB | NIW*256MB Aligned | 4 GB | NIW*256MB Aligned | 12 |
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+--------+------------+-------------------+------------------+-------------------+------+
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HDM decoder base and HDM decoder size represent all the 12 Endpoint Decoders of
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a 12 ways region and all the intermediate Switch Decoders. They are configured
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by the BIOS according to the NIW * 256MB rule, resulting in a HPA range size of
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3GB. Instead, the CFMWS Base and CFMWS Size are used to configure the Root
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Decoder HPA range that results smaller (2GB) than that of the Switch and
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Endpoint Decoders in the hierarchy (3GB).
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This creates 2 issues which lead to a failure to construct a region:
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1) A mismatch in region size between root and any HDM decoder. The root decoders
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will always be smaller due to the trim.
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2) The trim causes the root decoder to violate the (NIW * 256MB) rule.
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This change allows a region with a base address of 0GB to bypass these checks to
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allow for region creation with the trimmed root decoder address range.
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This change does not allow for any other arbitrary region to violate these
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checks - it is intended exclusively to enable x86 platforms which map CXL memory
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under 4GB.
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Despite the HDM decoders covering the PCIE hole HPA region, it is expected that
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the platform will never route address accesses to the CXL complex because the
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root decoder only covers the trimmed region (which excludes this). This is
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outside the ability of Linux to enforce.
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On the example platform, only the first 2GB will be potentially usable, but
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Linux, aiming to adhere to the current specifications, fails to construct
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Regions and attach Endpoint and intermediate Switch Decoders to them.
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There are several points of failure that due to the expectation that the Root
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Decoder HPA size, that is equal to the CFMWS from which it is configured, has
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to be greater or equal to the matching Switch and Endpoint HDM Decoders.
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In order to succeed with construction and attachment, Linux must construct a
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Region with Root Decoder HPA range size, and then attach to that all the
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intermediate Switch Decoders and Endpoint Decoders that belong to the hierarchy
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regardless of their range sizes.
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Benefits of the Change
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----------------------
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Without the change, the OSPM wouldn't match intermediate Switch and Endpoint
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Decoders with Root Decoders configured with CFMWS HPA sizes that don't align
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with the NIW * 256MB constraint, and so it leads to lost memdev capacity.
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This change allows the OSPM to construct Regions and attach intermediate Switch
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and Endpoint Decoders to them, so that the addressable part of the memory
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devices total capacity is made available to the users.
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References
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----------
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Compute Express Link Specification Revision 3.2, Version 1.0
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<https://www.computeexpresslink.org/>
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|
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|||
|
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Detailed Description of the Change
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----------------------------------
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The description of the Window Size field in table 9-22 needs to account for
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platforms with Low Memory Holes, where SPA ranges might be subsets of the
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endpoints HPA. Therefore, it has to be changed to the following:
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"The total number of consecutive bytes of HPA this window represents. This value
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shall be a multiple of NIW * 256 MB.
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On platforms that reserve physical addresses below 4 GB, such as the Low Memory
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Hole for PCIe MMIO on x86, an instance of CFMWS whose Base HPA range is 0 might
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have a size that doesn't align with the NIW * 256 MB constraint.
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Note that the matching intermediate Switch Decoders and the Endpoint Decoders
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HPA range sizes must still align to the above-mentioned rule, but the memory
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capacity that exceeds the CFMWS window size won't be accessible.".
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