265 lines
6.7 KiB
C
265 lines
6.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
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#ifndef _HINIC3_HW_INTF_H_
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#define _HINIC3_HW_INTF_H_
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#include <linux/bits.h>
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#include <linux/types.h>
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#define MGMT_MSG_CMD_OP_SET 1
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#define MGMT_MSG_CMD_OP_GET 0
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#define MGMT_STATUS_PF_SET_VF_ALREADY 0x4
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#define MGMT_STATUS_EXIST 0x6
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#define MGMT_STATUS_CMD_UNSUPPORTED 0xFF
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#define MGMT_MSG_POLLING_TIMEOUT 0
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struct mgmt_msg_head {
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u8 status;
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u8 version;
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u8 rsvd0[6];
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};
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struct mgmt_msg_params {
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const void *buf_in;
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u32 in_size;
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void *buf_out;
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u32 expected_out_size;
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u32 timeout_ms;
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};
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/* CMDQ MODULE_TYPE */
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enum mgmt_mod_type {
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/* HW communication module */
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MGMT_MOD_COMM = 0,
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/* L2NIC module */
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MGMT_MOD_L2NIC = 1,
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/* Configuration module */
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MGMT_MOD_CFGM = 7,
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MGMT_MOD_HILINK = 14,
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};
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static inline void mgmt_msg_params_init_default(struct mgmt_msg_params *msg_params,
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void *inout_buf, u32 buf_size)
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{
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msg_params->buf_in = inout_buf;
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msg_params->buf_out = inout_buf;
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msg_params->in_size = buf_size;
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msg_params->expected_out_size = buf_size;
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msg_params->timeout_ms = 0;
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}
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enum cfg_cmd {
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CFG_CMD_GET_DEV_CAP = 0,
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};
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/* Device capabilities, defined by hw */
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struct cfg_cmd_dev_cap {
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struct mgmt_msg_head head;
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u16 func_id;
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u16 rsvd1;
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/* Public resources */
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u8 host_id;
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u8 ep_id;
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u8 er_id;
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u8 port_id;
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u16 host_total_func;
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u8 host_pf_num;
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u8 pf_id_start;
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u16 host_vf_num;
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u16 vf_id_start;
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u8 host_oq_id_mask_val;
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u8 timer_en;
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u8 host_valid_bitmap;
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u8 rsvd_host;
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u16 svc_cap_en;
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u16 max_vf;
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u8 flexq_en;
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u8 valid_cos_bitmap;
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u8 port_cos_valid_bitmap;
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u8 rsvd2[45];
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/* l2nic */
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u16 nic_max_sq_id;
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u16 nic_max_rq_id;
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u16 nic_default_num_queues;
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u8 rsvd3[250];
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};
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/* COMM Commands between Driver to fw */
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enum comm_cmd {
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/* Commands for clearing FLR and resources */
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COMM_CMD_FUNC_RESET = 0,
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COMM_CMD_FEATURE_NEGO = 1,
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COMM_CMD_FLUSH_DOORBELL = 2,
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COMM_CMD_START_FLUSH = 3,
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COMM_CMD_GET_GLOBAL_ATTR = 5,
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COMM_CMD_SET_FUNC_SVC_USED_STATE = 7,
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/* Driver Configuration Commands */
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COMM_CMD_SET_CMDQ_CTXT = 20,
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COMM_CMD_SET_VAT = 21,
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COMM_CMD_CFG_PAGESIZE = 22,
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COMM_CMD_CFG_MSIX_CTRL_REG = 23,
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COMM_CMD_SET_CEQ_CTRL_REG = 24,
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COMM_CMD_SET_DMA_ATTR = 25,
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};
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struct comm_cmd_cfg_msix_ctrl_reg {
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struct mgmt_msg_head head;
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u16 func_id;
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u8 opcode;
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u8 rsvd1;
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u16 msix_index;
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u8 pending_cnt;
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u8 coalesce_timer_cnt;
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u8 resend_timer_cnt;
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u8 lli_timer_cnt;
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u8 lli_credit_cnt;
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u8 rsvd2[5];
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};
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enum comm_func_reset_bits {
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COMM_FUNC_RESET_BIT_FLUSH = BIT(0),
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COMM_FUNC_RESET_BIT_MQM = BIT(1),
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COMM_FUNC_RESET_BIT_SMF = BIT(2),
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COMM_FUNC_RESET_BIT_PF_BW_CFG = BIT(3),
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COMM_FUNC_RESET_BIT_COMM = BIT(10),
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/* clear mbox and aeq, The COMM_FUNC_RESET_BIT_COMM bit must be set */
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COMM_FUNC_RESET_BIT_COMM_MGMT_CH = BIT(11),
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/* clear cmdq and ceq, The COMM_FUNC_RESET_BIT_COMM bit must be set */
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COMM_FUNC_RESET_BIT_COMM_CMD_CH = BIT(12),
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COMM_FUNC_RESET_BIT_NIC = BIT(13),
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};
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#define COMM_FUNC_RESET_FLAG \
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(COMM_FUNC_RESET_BIT_COMM | COMM_FUNC_RESET_BIT_COMM_CMD_CH | \
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COMM_FUNC_RESET_BIT_FLUSH | COMM_FUNC_RESET_BIT_MQM | \
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COMM_FUNC_RESET_BIT_SMF | COMM_FUNC_RESET_BIT_PF_BW_CFG)
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struct comm_cmd_func_reset {
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struct mgmt_msg_head head;
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u16 func_id;
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u16 rsvd1[3];
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u64 reset_flag;
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};
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#define COMM_MAX_FEATURE_QWORD 4
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struct comm_cmd_feature_nego {
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struct mgmt_msg_head head;
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u16 func_id;
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u8 opcode;
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u8 rsvd;
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u64 s_feature[COMM_MAX_FEATURE_QWORD];
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};
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struct comm_global_attr {
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u8 max_host_num;
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u8 max_pf_num;
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u16 vf_id_start;
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/* for api cmd to mgmt cpu */
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u8 mgmt_host_node_id;
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u8 cmdq_num;
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u8 rsvd1[34];
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};
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struct comm_cmd_get_glb_attr {
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struct mgmt_msg_head head;
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struct comm_global_attr attr;
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};
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enum comm_func_svc_type {
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COMM_FUNC_SVC_T_COMM = 0,
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COMM_FUNC_SVC_T_NIC = 1,
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};
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struct comm_cmd_set_func_svc_used_state {
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struct mgmt_msg_head head;
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u16 func_id;
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u16 svc_type;
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u8 used_state;
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u8 rsvd[35];
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};
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struct comm_cmd_set_dma_attr {
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struct mgmt_msg_head head;
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u16 func_id;
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u8 entry_idx;
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u8 st;
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u8 at;
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u8 ph;
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u8 no_snooping;
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u8 tph_en;
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u32 resv1;
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};
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struct comm_cmd_set_ceq_ctrl_reg {
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struct mgmt_msg_head head;
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u16 func_id;
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u16 q_id;
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u32 ctrl0;
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u32 ctrl1;
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u32 rsvd1;
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};
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struct comm_cmd_cfg_wq_page_size {
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struct mgmt_msg_head head;
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u16 func_id;
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u8 opcode;
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/* real_size=4KB*2^page_size, range(0~20) must be checked by driver */
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u8 page_size;
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u32 rsvd1;
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};
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struct comm_cmd_set_root_ctxt {
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struct mgmt_msg_head head;
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u16 func_id;
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u8 set_cmdq_depth;
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u8 cmdq_depth;
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u16 rx_buf_sz;
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u8 lro_en;
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u8 rsvd1;
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u16 sq_depth;
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u16 rq_depth;
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u64 rsvd2;
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};
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struct comm_cmdq_ctxt_info {
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__le64 curr_wqe_page_pfn;
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__le64 wq_block_pfn;
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};
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struct comm_cmd_set_cmdq_ctxt {
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struct mgmt_msg_head head;
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u16 func_id;
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u8 cmdq_id;
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u8 rsvd1[5];
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struct comm_cmdq_ctxt_info ctxt;
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};
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struct comm_cmd_clear_resource {
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struct mgmt_msg_head head;
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u16 func_id;
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u16 rsvd1[3];
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};
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/* Services supported by HW. HW uses these values when delivering events.
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* HW supports multiple services that are not yet supported by driver
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* (e.g. RoCE).
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*/
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enum hinic3_service_type {
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HINIC3_SERVICE_T_NIC = 0,
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/* MAX is only used by SW for array sizes. */
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HINIC3_SERVICE_T_MAX = 1,
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};
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#endif
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