139 lines
2.8 KiB
C
139 lines
2.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
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* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
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*/
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#ifndef _DT_BINDINGS_STM32MP21_RESET_H_
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#define _DT_BINDINGS_STM32MP21_RESET_H_
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#define TIM1_R 0
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#define TIM2_R 1
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#define TIM3_R 2
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#define TIM4_R 3
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#define TIM5_R 4
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#define TIM6_R 5
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#define TIM7_R 6
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#define TIM8_R 7
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#define TIM10_R 8
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#define TIM11_R 9
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#define TIM12_R 10
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#define TIM13_R 11
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#define TIM14_R 12
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#define TIM15_R 13
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#define TIM16_R 14
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#define TIM17_R 15
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#define LPTIM1_R 16
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#define LPTIM2_R 17
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#define LPTIM3_R 18
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#define LPTIM4_R 19
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#define LPTIM5_R 20
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#define SPI1_R 21
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#define SPI2_R 22
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#define SPI3_R 23
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#define SPI4_R 24
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#define SPI5_R 25
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#define SPI6_R 26
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#define SPDIFRX_R 27
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#define USART1_R 28
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#define USART2_R 29
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#define USART3_R 30
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#define UART4_R 31
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#define UART5_R 32
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#define USART6_R 33
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#define UART7_R 34
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#define LPUART1_R 35
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#define I2C1_R 36
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#define I2C2_R 37
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#define I2C3_R 38
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#define SAI1_R 39
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#define SAI2_R 40
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#define SAI3_R 41
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#define SAI4_R 42
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#define MDF1_R 43
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#define FDCAN_R 44
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#define HDP_R 45
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#define ADC1_R 46
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#define ADC2_R 47
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#define ETH1_R 48
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#define ETH2_R 49
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#define USBH_R 50
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#define USB2PHY1_R 51
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#define USB2PHY2_R 52
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#define SDMMC1_R 53
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#define SDMMC1DLL_R 54
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#define SDMMC2_R 55
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#define SDMMC2DLL_R 56
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#define SDMMC3_R 57
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#define SDMMC3DLL_R 58
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#define LTDC_R 59
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#define CSI_R 60
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#define DCMIPP_R 61
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#define DCMIPSSI_R 62
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#define WWDG1_R 63
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#define VREF_R 64
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#define DTS_R 65
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#define CRC_R 66
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#define SERC_R 67
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#define I3C1_R 68
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#define I3C2_R 69
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#define I3C3_R 70
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#define IWDG2_KER_R 71
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#define IWDG4_KER_R 72
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#define RNG1_R 73
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#define RNG2_R 74
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#define PKA_R 75
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#define SAES_R 76
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#define HASH1_R 77
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#define HASH2_R 78
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#define CRYP1_R 79
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#define CRYP2_R 80
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#define OSPI1_R 81
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#define OSPI1DLL_R 82
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#define OTG_R 83
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#define FMC_R 84
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#define DBG_R 85
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#define GPIOA_R 86
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#define GPIOB_R 87
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#define GPIOC_R 88
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#define GPIOD_R 89
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#define GPIOE_R 90
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#define GPIOF_R 91
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#define GPIOG_R 92
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#define GPIOH_R 93
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#define GPIOI_R 94
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#define GPIOZ_R 95
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#define HPDMA1_R 96
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#define HPDMA2_R 97
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#define HPDMA3_R 98
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#define IPCC1_R 99
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#define C2_HOLDBOOT_R 100
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#define C1_HOLDBOOT_R 101
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#define C1_R 102
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#define C1P1POR_R 103
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#define C1P1_R 104
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#define C2_R 105
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#define SYS_R 106
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#define VSW_R 107
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#define C1MS_R 108
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#define DDRCP_R 109
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#define DDRCAPB_R 110
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#define DDRPHYCAPB_R 111
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#define DDRCFG_R 112
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#define DDR_R 113
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#define DDRPERFM_R 114
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#define IWDG1_SYS_R 116
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#define IWDG2_SYS_R 117
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#define IWDG3_SYS_R 118
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#define IWDG4_SYS_R 119
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#define RST_SCMI_C1_R 0
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#define RST_SCMI_C2_R 1
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#define RST_SCMI_C1_HOLDBOOT_R 2
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#define RST_SCMI_C2_HOLDBOOT_R 3
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#define RST_SCMI_FMC 4
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#define RST_SCMI_OSPI1 5
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#define RST_SCMI_OSPI1DLL 6
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#endif /* _DT_BINDINGS_STM32MP21_RESET_H_ */
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