28 lines
962 B
C
28 lines
962 B
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Microchip SAMA7 SFRBU registers offsets and bit definitions.
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*
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* Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries
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*
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* Author: Claudu Beznea <claudiu.beznea@microchip.com>
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*/
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#ifndef __SAMA7_SFRBU_H__
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#define __SAMA7_SFRBU_H__
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#ifdef CONFIG_SOC_SAMA7
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#define AT91_SFRBU_PSWBU (0x00) /* SFRBU Power Switch BU Control Register */
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#define AT91_SFRBU_PSWBU_PSWKEY (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */
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#define AT91_SFRBU_PSWBU_STATE (1 << 2) /* Power switch BU state */
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#define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */
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#define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */
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#define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */
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#define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */
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#endif /* CONFIG_SOC_SAMA7 */
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#endif /* __SAMA7_SFRBU_H__ */
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