195 lines
9.1 KiB
ReStructuredText
195 lines
9.1 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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===============================================
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PPE Ethernet Driver for Qualcomm IPQ SoC Family
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===============================================
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Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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Author: Lei Wei <quic_leiwei@quicinc.com>
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Contents
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========
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- `PPE Overview`_
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- `PPE Driver Overview`_
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- `PPE Driver Supported SoCs`_
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- `Enabling the Driver`_
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- `Debugging`_
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PPE Overview
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============
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IPQ (Qualcomm Internet Processor) SoC (System-on-Chip) series is Qualcomm's series of
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networking SoC for Wi-Fi access points. The PPE (Packet Process Engine) is the Ethernet
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packet process engine in the IPQ SoC.
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Below is a simplified hardware diagram of IPQ9574 SoC which includes the PPE engine and
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other blocks which are in the SoC but outside the PPE engine. These blocks work together
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to enable the Ethernet for the IPQ SoC::
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+------+ +------+ +------+ +------+ +------+ +------+ start +-------+
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|netdev| |netdev| |netdev| |netdev| |netdev| |netdev|<------|PHYLINK|
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+------+ +------+ +------+ +------+ +------+ +------+ stop +-+-+-+-+
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| | | ^
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+-------+ +-------------------------+--------+----------------------+ | | |
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| GCC | | | EDMA | | | | |
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+---+---+ | PPE +---+----+ | | | |
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| clk | | | | | |
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+-------->| +-----------------------+------+-----+---------------+ | | | |
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| | Switch Core |Port0 | |Port7(EIP FIFO)| | | | |
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| | +---+--+ +------+--------+ | | | |
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| | | | | | | | |
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+-------+ | | +------+---------------+----+ | | | | |
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|CMN PLL| | | +---+ +---+ +----+ | +--------+ | | | | | |
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+---+---+ | | |BM | |QM | |SCH | | | L2/L3 | ....... | | | | | |
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| | | | +---+ +---+ +----+ | +--------+ | | | | | |
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| | | | +------+--------------------+ | | | | |
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| | | | | | | | | |
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| v | | +-----+-+-----+-+-----+-+-+---+--+-----+-+-----+ | | | | |
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| +------+ | | |Port1| |Port2| |Port3| |Port4| |Port5| |Port6| | | | | |
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| |NSSCC | | | +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ | | mac| | |
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| +-+-+--+ | | |MAC0 | |MAC1 | |MAC2 | |MAC3 | |MAC4 | |MAC5 | | |<---+ | |
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| ^ | |clk | | +-----+-+-----+-+-----+-+-----+--+-----+-+-----+ | | ops | |
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| | | +------>| +----|------|-------|-------|---------|--------|-----+ | | |
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| | | +---------------------------------------------------------+ | |
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| | | | | | | | | | |
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| | | MII clk | QSGMII USXGMII USXGMII | |
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| | +--------------->| | | | | | | |
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| | +-------------------------+ +---------+ +---------+ | |
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| |125/312.5MHz clk| (PCS0) | | (PCS1) | | (PCS2) | pcs ops | |
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| +----------------+ UNIPHY0 | | UNIPHY1 | | UNIPHY2 |<--------+ |
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+----------------->| | | | | | |
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| 31.25MHz ref clk +-------------------------+ +---------+ +---------+ |
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| | | | | | | |
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| +-----------------------------------------------------+ |
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|25/50MHz ref clk| +-------------------------+ +------+ +------+ | link |
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+--------------->| | QUAD PHY | | PHY4 | | PHY5 | |---------+
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| +-------------------------+ +------+ +------+ | change
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| MDIO bus |
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+-----------------------------------------------------+
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The CMN (Common) PLL, NSSCC (Networking Sub System Clock Controller) and GCC (Global
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Clock Controller) blocks are in the SoC and act as clock providers.
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The UNIPHY block is in the SoC and provides the PCS (Physical Coding Sublayer) and
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XPCS (10-Gigabit Physical Coding Sublayer) functions to support different interface
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modes between the PPE MAC and the external PHY.
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This documentation focuses on the descriptions of PPE engine and the PPE driver.
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The Ethernet functionality in the PPE (Packet Process Engine) is comprised of three
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components: the switch core, port wrapper and Ethernet DMA.
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The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and two FIFO
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interfaces. One of the two FIFO interfaces is used for Ethernet port to host CPU
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communication using Ethernet DMA. The other one is used to communicate to the EIP
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engine which is used for IPsec offload. On the IPQ9574, the PPE includes 6 GMAC/XGMACs
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that can be connected with external Ethernet PHY. Switch core also includes BM (Buffer
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Management), QM (Queue Management) and SCH (Scheduler) modules for supporting the
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packet processing.
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The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) supporting
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various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There are 3 UNIPHY (PCS)
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instances supported on the IPQ9574.
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Ethernet DMA is used to transmit and receive packets between the Ethernet subsystem
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and ARM host CPU.
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The following lists the main blocks in the PPE engine which will be driven by this
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PPE driver:
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- BM
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BM is the hardware buffer manager for the PPE switch ports.
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- QM
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Queue Manager for managing the egress hardware queues of the PPE switch ports.
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- SCH
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The scheduler which manages the hardware traffic scheduling for the PPE switch ports.
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- L2
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The L2 block performs the packet bridging in the switch core. The bridge domain is
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represented by the VSI (Virtual Switch Instance) domain in PPE. FDB learning can be
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enabled based on the VSI domain and bridge forwarding occurs within the VSI domain.
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- MAC
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The PPE in the IPQ9574 supports up to six MACs (MAC0 to MAC5) which are corresponding
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to six switch ports (port1 to port6). The MAC block is connected with external PHY
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through the UNIPHY PCS block. Each MAC block includes the GMAC and XGMAC blocks and
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the switch port can select to use GMAC or XMAC through a MUX selection according to
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the external PHY's capability.
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- EDMA (Ethernet DMA)
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The Ethernet DMA is used to transmit and receive Ethernet packets between the PPE
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ports and the ARM cores.
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The received packet on a PPE MAC port can be forwarded to another PPE MAC port. It can
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be also forwarded to internal switch port0 so that the packet can be delivered to the
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ARM cores using the Ethernet DMA (EDMA) engine. The Ethernet DMA driver will deliver the
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packet to the corresponding 'netdevice' interface.
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The software instantiations of the PPE MAC (netdevice), PCS and external PHYs interact
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with the Linux PHYLINK framework to manage the connectivity between the PPE ports and
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the connected PHYs, and the port link states. This is also illustrated in above diagram.
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PPE Driver Overview
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===================
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PPE driver is Ethernet driver for the Qualcomm IPQ SoC. It is a single platform driver
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which includes the PPE part and Ethernet DMA part. The PPE part initializes and drives the
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various blocks in PPE switch core such as BM/QM/L2 blocks and the PPE MACs. The EDMA part
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drives the Ethernet DMA for packet transfer between PPE ports and ARM cores, and enables
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the netdevice driver for the PPE ports.
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The PPE driver files in drivers/net/ethernet/qualcomm/ppe/ are listed as below:
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- Makefile
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- ppe.c
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- ppe.h
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- ppe_config.c
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- ppe_config.h
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- ppe_debugfs.c
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- ppe_debugfs.h
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- ppe_regs.h
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The ppe.c file contains the main PPE platform driver and undertakes the initialization of
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PPE switch core blocks such as QM, BM and L2. The configuration APIs for these hardware
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blocks are provided in the ppe_config.c file.
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The ppe.h defines the PPE device data structure which will be used by PPE driver functions.
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The ppe_debugfs.c enables the PPE statistics counters such as PPE port Rx and Tx counters,
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CPU code counters and queue counters.
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PPE Driver Supported SoCs
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=========================
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The PPE driver supports the following IPQ SoC:
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- IPQ9574
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Enabling the Driver
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===================
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The driver is located in the menu structure at::
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-> Device Drivers
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-> Network device support (NETDEVICES [=y])
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-> Ethernet driver support
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-> Qualcomm devices
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-> Qualcomm Technologies, Inc. PPE Ethernet support
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If the driver is built as a module, the module will be called qcom-ppe.
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The PPE driver functionally depends on the CMN PLL and NSSCC clock controller drivers.
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Please make sure the dependent modules are installed before installing the PPE driver
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module.
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Debugging
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=========
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The PPE hardware counters can be accessed using debugfs interface from the
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``/sys/kernel/debug/ppe/`` directory.
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