84 lines
1.7 KiB
Plaintext
84 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2025 Josua Mayer <josua@solid-run.com>
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*/
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/dts-v1/;
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include "imx8mp-sr-som.dtsi"
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#include "imx8mp-hummingboard-pulse-codec.dtsi"
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#include "imx8mp-hummingboard-pulse-common.dtsi"
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#include "imx8mp-hummingboard-pulse-hdmi.dtsi"
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#include "imx8mp-hummingboard-pulse-m2con.dtsi"
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#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi"
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/ {
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model = "SolidRun i.MX8MP HummingBoard Pulse";
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compatible = "solidrun,imx8mp-hummingboard-pulse",
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"solidrun,imx8mp-sr-som", "fsl,imx8mp";
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aliases {
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ethernet0 = &eqos;
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ethernet1 = &pcie_eth;
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};
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};
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&fec {
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/* this board does not use second phy / ethernet on SoM */
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status = "disabled";
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};
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&gpio1 {
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pinctrl-0 = <&mpcie_reset_pins>, <&m2_reset_pins>;
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pinctrl-names = "default";
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m2-reset-hog {
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gpio-hog;
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gpios = <6 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "m2-reset";
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&hdmi_pins>,
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<&m2_wwan_wake_pins>;
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pcie_eth_pins: pinctrl-pcie-eth-grp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x0
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>;
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};
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};
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&pcie {
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pinctrl-0 = <&pcie_eth_pins>;
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pinctrl-names = "default";
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reset-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
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status = "okay";
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root@0,0 {
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compatible = "pci16c3,abcd";
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reg = <0x00000000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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/* Intel i210 */
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pcie_eth: ethernet@1,0 {
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compatible = "pci8086,157b";
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reg = <0x00010000 0 0 0 0>;
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};
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};
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};
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&pcie_phy {
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clocks = <&hsio_blk_ctrl>;
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clock-names = "ref";
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fsl,clkreq-unsupported;
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fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
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status = "okay";
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};
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