162 lines
3.4 KiB
Plaintext
162 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022,2025 NXP
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*/
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#include "imx91_93_common.dtsi"
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/{
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cm33: remoteproc-cm33 {
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compatible = "fsl,imx93-cm33";
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clocks = <&clk IMX93_CLK_CM33_GATE>;
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status = "disabled";
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};
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thermal-zones {
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cpu-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tmu 0>;
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trips {
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cpu_alert: cpu-alert {
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temperature = <80000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu-crit {
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temperature = <90000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert>;
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cooling-device =
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<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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};
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&aips1 {
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mu1: mailbox@44230000 {
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compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
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reg = <0x44230000 0x10000>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_MU1_B_GATE>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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tmu: tmu@44482000 {
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compatible = "fsl,qoriq-tmu";
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reg = <0x44482000 0x1000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_TMC_GATE>;
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#thermal-sensor-cells = <1>;
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little-endian;
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fsl,tmu-range = <0x800000da 0x800000e9
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0x80000102 0x8000012a
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0x80000166 0x800001a7
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0x800001b6>;
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fsl,tmu-calibration = <0x00000000 0x0000000e
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0x00000001 0x00000029
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0x00000002 0x00000056
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0x00000003 0x000000a2
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0x00000004 0x00000116
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0x00000005 0x00000195
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0x00000006 0x000001b2>;
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};
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};
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&aips2 {
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mu2: mailbox@42440000 {
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compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
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reg = <0x42440000 0x10000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_MU2_B_GATE>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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};
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&cpus {
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A55_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0>;
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enable-method = "psci";
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#cooling-cells = <2>;
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cpu-idle-states = <&cpu_pd_wait>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_cache_l0>;
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};
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A55_1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x100>;
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enable-method = "psci";
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#cooling-cells = <2>;
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cpu-idle-states = <&cpu_pd_wait>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_cache_l1>;
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};
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l2_cache_l0: l2-cache-l0 {
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compatible = "cache";
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cache-size = <65536>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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l2_cache_l1: l2-cache-l1 {
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compatible = "cache";
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cache-size = <65536>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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l3_cache: l3-cache {
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compatible = "cache";
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cache-size = <262144>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-level = <3>;
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cache-unified;
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};
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};
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&src {
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mlmix: power-domain@44461800 {
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compatible = "fsl,imx93-src-slice";
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reg = <0x44461800 0x400>, <0x44464800 0x400>;
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clocks = <&clk IMX93_CLK_ML_APB>,
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<&clk IMX93_CLK_ML>;
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#power-domain-cells = <0>;
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};
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};
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