405 lines
8.4 KiB
Plaintext
405 lines
8.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the R9A09G047E57 SMARC SoM board.
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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/*
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* Please set the below switch position on the SoM and the corresponding macro
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* on the board DTS:
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*
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* Switch position SYS.1, Macro SW_SD0_DEV_SEL:
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* 0 - SD0 is connected to eMMC (default)
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* 1 - SD0 is connected to uSD0 card
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*
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* Switch position SYS.5, Macro SW_LCD_EN:
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* 0 - Select Misc. Signals routing
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* 1 - Select LCD
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*
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* Switch position BOOT.6, Macro SW_PDM_EN:
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* 0 - Select CAN routing
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* 1 - Select PDM
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*/
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/ {
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compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
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aliases {
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ethernet0 = ð0;
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ethernet1 = ð1;
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i2c2 = &i2c2;
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mmc0 = &sdhi0;
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mmc2 = &sdhi2;
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};
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memory@48000000 {
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device_type = "memory";
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/* First 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0xf8000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_vdd0p8v_others: regulator-vdd0p8v-others {
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compatible = "regulator-fixed";
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regulator-name = "fixed-0.8V";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* 32.768kHz crystal */
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x3: x3-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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&audio_extal_clk {
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clock-frequency = <48000000>;
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};
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ð0 {
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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pinctrl-0 = <ð0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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ð1 {
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phy-handle = <&phy1>;
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phy-mode = "rgmii-id";
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pinctrl-0 = <ð1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&gpu {
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status = "okay";
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mali-supply = <®_vdd0p8v_others>;
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};
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&i2c2 {
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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raa215300: pmic@12 {
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compatible = "renesas,raa215300";
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reg = <0x12>, <0x6f>;
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reg-names = "main", "rtc";
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clocks = <&x3>;
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clock-names = "xin";
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pinctrl-0 = <&rtc_irq_pin>;
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pinctrl-names = "default";
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interrupts-extended = <&pinctrl RZG3E_GPIO(S, 1) IRQ_TYPE_EDGE_FALLING>;
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};
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};
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&mdio0 {
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phy0: ethernet-phy@7 {
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compatible = "ethernet-phy-id0022.1640",
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"ethernet-phy-ieee802.3-c22";
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reg = <7>;
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interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
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rxc-skew-psec = <1400>;
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txc-skew-psec = <1400>;
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rxdv-skew-psec = <0>;
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txdv-skew-psec = <0>;
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rxd0-skew-psec = <0>;
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rxd1-skew-psec = <0>;
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rxd2-skew-psec = <0>;
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rxd3-skew-psec = <0>;
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txd0-skew-psec = <0>;
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txd1-skew-psec = <0>;
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txd2-skew-psec = <0>;
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txd3-skew-psec = <0>;
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};
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};
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&mdio1 {
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phy1: ethernet-phy@7 {
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compatible = "ethernet-phy-id0022.1640",
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"ethernet-phy-ieee802.3-c22";
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reg = <7>;
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interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>;
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rxc-skew-psec = <1400>;
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txc-skew-psec = <1400>;
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rxdv-skew-psec = <0>;
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txdv-skew-psec = <0>;
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rxd0-skew-psec = <0>;
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rxd1-skew-psec = <0>;
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rxd2-skew-psec = <0>;
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rxd3-skew-psec = <0>;
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txd0-skew-psec = <0>;
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txd1-skew-psec = <0>;
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txd2-skew-psec = <0>;
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txd3-skew-psec = <0>;
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};
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};
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&pinctrl {
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eth0_pins: eth0 {
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clk {
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pinmux = <RZG3E_PORT_PINMUX(B, 1, 1)>; /* TXC */
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output-enable;
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};
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ctrl {
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pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
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<RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
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<RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
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<RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
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<RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
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<RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
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<RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
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<RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
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<RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
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<RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
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<RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
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<RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
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<RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
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<RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
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};
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};
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eth1_pins: eth1 {
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clk {
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pinmux = <RZG3E_PORT_PINMUX(E, 1, 1)>; /* TXC */
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output-enable;
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};
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ctrl {
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pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
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<RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
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<RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
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<RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
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<RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
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<RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
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<RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
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<RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
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<RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
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<RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
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<RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
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<RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
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<RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
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<RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
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};
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};
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i2c2_pins: i2c {
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pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
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<RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
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};
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rtc_irq_pin: rtc-irq {
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pins = "PS1";
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bias-pull-up;
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};
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sdhi0_emmc_pins: sd0-emmc {
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sd0-ctrl {
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pins = "SD0CLK", "SD0CMD";
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renesas,output-impedance = <3>;
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};
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sd0-data {
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pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3",
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"SD0DAT4", "SD0DAT5", "SD0DAT6", "SD0DAT7";
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renesas,output-impedance = <3>;
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};
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sd0-rst {
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pins = "SD0RSTN";
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renesas,output-impedance = <3>;
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};
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};
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sdhi0_usd_pins: sd0-usd {
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sd0-cd {
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pinmux = <RZG3E_PORT_PINMUX(5, 0, 8)>;
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};
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sd0-ctrl {
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pins = "SD0CLK", "SD0CMD";
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renesas,output-impedance = <3>;
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};
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sd0-data {
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pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3";
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renesas,output-impedance = <3>;
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};
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sd0-iovs {
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pins = "SD0IOVS";
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renesas,output-impedance = <3>;
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};
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sd0-pwen {
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pins = "SD0PWEN";
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renesas,output-impedance = <3>;
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};
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};
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sdhi2_pins: sd2 {
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sd2-cd {
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pinmux = <RZG3E_PORT_PINMUX(K, 0, 1)>; /* SD2CD */
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};
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sd2-ctrl {
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pinmux = <RZG3E_PORT_PINMUX(H, 0, 1)>, /* SD2CLK */
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<RZG3E_PORT_PINMUX(H, 1, 1)>; /* SD2CMD */
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};
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sd2-data {
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pinmux = <RZG3E_PORT_PINMUX(H, 2, 1)>, /* SD2DAT0 */
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<RZG3E_PORT_PINMUX(H, 3, 1)>, /* SD2DAT1 */
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<RZG3E_PORT_PINMUX(H, 4, 1)>, /* SD2DAT2 */
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<RZG3E_PORT_PINMUX(H, 5, 1)>; /* SD2DAT3 */
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};
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sd2-iovs {
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pinmux = <RZG3E_PORT_PINMUX(K, 1, 1)>; /* SD2IOVS */
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};
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sd2-pwen {
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pinmux = <RZG3E_PORT_PINMUX(K, 2, 1)>; /* SD2PWEN */
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};
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};
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xspi_pins: xspi0 {
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pinmux = <RZG3E_PORT_PINMUX(M, 0, 0)>, /* XSPI0_IO0 */
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<RZG3E_PORT_PINMUX(M, 1, 0)>, /* XSPI0_IO1 */
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<RZG3E_PORT_PINMUX(M, 2, 0)>, /* XSPI0_IO2 */
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<RZG3E_PORT_PINMUX(M, 3, 0)>, /* XSPI0_IO3 */
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<RZG3E_PORT_PINMUX(L, 0, 0)>, /* XSPI0_CKP */
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<RZG3E_PORT_PINMUX(L, 1, 0)>; /* XSPI0_CS0 */
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};
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};
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&qextal_clk {
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clock-frequency = <24000000>;
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};
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&rtxin_clk {
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clock-frequency = <32768>;
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};
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#if (SW_SD0_DEV_SEL)
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&sdhi0 {
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pinctrl-0 = <&sdhi0_usd_pins>;
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pinctrl-1 = <&sdhi0_usd_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <&sdhi0_vqmmc>;
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bus-width = <4>;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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&sdhi0_vqmmc {
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status = "okay";
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};
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#else
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&sdhi0 {
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pinctrl-0 = <&sdhi0_emmc_pins>;
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pinctrl-1 = <&sdhi0_emmc_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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bus-width = <8>;
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mmc-hs200-1_8v;
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non-removable;
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fixed-emmc-driver-type = <1>;
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status = "okay";
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};
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#endif
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&sdhi2 {
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pinctrl-0 = <&sdhi2_pins>;
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pinctrl-1 = <&sdhi2_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <&sdhi2_vqmmc>;
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bus-width = <4>;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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&sdhi2_vqmmc {
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status = "okay";
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};
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&wdt1 {
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status = "okay";
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};
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&xspi {
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pinctrl-0 = <&xspi_pins>;
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pinctrl-names = "default";
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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vcc-supply = <®_1p8v>;
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m25p,fast-read;
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bl2";
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reg = <0x00000000 0x00060000>;
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};
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partition@60000 {
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label = "fip";
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reg = <0x00060000 0x007a0000>;
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};
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partition@800000 {
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label = "user";
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reg = <0x800000 0x800000>;
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};
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};
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};
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};
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