172 lines
5.8 KiB
Plaintext
172 lines
5.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Copyright (c) 2024 Cherry Embedded Solutions GmbH
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*
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* Device Tree Overlay for the Pre-ICT tester adapter for the Mezzanine
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* connector on RK3588 Jaguar.
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*
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* This adapter has a PCIe Gen2 x1 M.2 M-Key connector and two proprietary
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* camera connectors (each their own I2C bus, clock, reset and PWM lines as well
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* as 2-lane CSI).
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*
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* This adapter routes some GPIOs to power rails and loops together some other
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* GPIOs.
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*
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* This adapter is used during manufacturing for validating proper soldering of
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* the mezzanine connector.
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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&{/} {
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pre_ict_tester_vcc_1v2: regulator-pre-ict-tester-vcc-1v2 {
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compatible = "regulator-fixed";
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regulator-name = "pre_ict_tester_vcc_1v2";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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vin-supply = <&vcc_3v3_s3>;
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};
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pre_ict_tester_vcc_2v8: regulator-pre-ict-tester-vcc-2v8 {
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compatible = "regulator-fixed";
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regulator-name = "pre_ict_tester_vcc_2v8";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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vin-supply = <&vcc_3v3_s3>;
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};
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};
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&combphy0_ps {
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status = "okay";
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};
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&gpio3 {
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pinctrl-0 = <&pre_ict_pwr2gpio>;
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pinctrl-names = "default";
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};
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&pcie2x1l2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie2x1l2_perstn_m0>;
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reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; /* PCIE20X1_2_PERSTN_M0 */
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vpcie3v3-supply = <&vcc_3v3_s3>;
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status = "okay";
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};
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&pinctrl {
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pcie2x1l2 {
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pcie2x1l2_perstn_m0: pcie2x1l2-perstn-m0 {
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rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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pre-ict-tester {
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pre_ict_pwr2gpio: pre-ict-pwr2gpio-pins {
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rockchip,pins =
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/*
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* GPIO3_A3 requires two power rails to be properly
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* routed to the mezzanine connector to report a proper
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* value: VCC_1V8_S0_1 and VCC_IN_2. It may report an
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* incorrect value if VCC_1V8_S0_1 isn't properly routed,
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* but GPIO3_C6 would catch this HW soldering issue.
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* If VCC_IN_2 is properly routed, GPIO3_A3 should be
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* LOW. The signal shall not read HIGH in the event
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* GPIO3_A3 isn't properly routed due to soldering
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* issue. Therefore, let's enforce a pull-up (which is
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* the SoC default for this pin).
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*/
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<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
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/*
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* GPIO3_A4 is directly routed to VCC_1V8_S0_2 power
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* rail. It should be HIGH if all is properly soldered.
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* To guarantee that, a pull-down is enforced (which is
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* the SoC default for this pin) so that LOW is read if
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* the loop doesn't exist on HW (soldering issue on
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* either signals).
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*/
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<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>,
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/*
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* GPIO3_B2 requires two power rails to be properly
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* routed to the mezzanine connector to report a proper
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* value: VCC_1V8_S0_1 and VCC_IN_1. It may report an
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* incorrect value if VCC_1V8_S0_1 isn't properly routed,
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* but GPIO3_C6 would catch this HW soldering issue.
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* If VCC_IN_1 is properly routed, GPIO3_B2 should be
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* LOW. This is an issue if GPIO3_B2 isn't properly
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* routed due to soldering issue, because GPIO3_B2
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* default bias is pull-down therefore being LOW. So
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* the worst case scenario and the pass scenario expect
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* the same value. Make GPIO3_B2 a pull-up so that a
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* soldering issue on GPIO3_B2 reports HIGH but proper
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* soldering reports LOW.
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*/
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<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
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/*
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* GPIO3_C6 is directly routed to VCC_1V8_S0_1 power
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* rail. It should be HIGH if all is properly soldered.
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* This is an issue if GPIO3_C6 or VCC_1V8_S0_1 isn't
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* properly routed due to soldering issue, because
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* GPIO3_C6 default bias is pull-up therefore being HIGH
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* in all cases:
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* - GPIO3_C6 is floating (so HIGH) if GPIO3_C6 is not
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* routed properly,
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* - GPIO3_C6 is floating (so HIGH) if VCC_1V8_S0_1 is
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* not routed properly,
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* - GPIO3_C6 is HIGH if everything is proper,
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* Make GPIO3_C6 a pull-down so that a soldering issue
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* on GPIO3_C6 or VCC_1V8_S0_1 reports LOW but proper
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* soldering reports HIGH.
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*/
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<3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>,
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/*
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* GPIO3_D2 is routed to VCC_5V0_1 power rail through a
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* voltage divider on the adapter.
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* It should be HIGH if all is properly soldered.
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* To guarantee that, a pull-down is enforced (which is
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* the SoC default for this pin) so that LOW is read if
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* the loop doesn't exist on HW (soldering issue on
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* either signals).
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*/
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<3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>,
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/*
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* GPIO3_D3 is routed to VCC_5V0_2 power rail through a
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* voltage divider on the adapter.
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* It should be HIGH if all is properly soldered.
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* To guarantee that, a pull-down is enforced (which is
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* the SoC default for this pin) so that LOW is read if
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* the loop doesn't exist on HW (soldering issue on
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* either signals).
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*/
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<3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>,
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/*
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* GPIO3_D4 is routed to VCC_3V3_S3_1 power rail through
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* a voltage divider on the adapter.
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* It should be HIGH if all is properly soldered.
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* To guarantee that, a pull-down is enforced (which is
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* the SoC default for this pin) so that LOW is read if
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* the loop doesn't exist on HW (soldering issue on
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* either signals).
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*/
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<3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>,
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/*
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* GPIO3_D5 is routed to VCC_3V3_S3_2 power rail through
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* a voltage divider on the adapter.
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* It should be HIGH if all is properly soldered.
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* To guarantee that, a pull-down is enforced (which is
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* the SoC default for this pin) so that LOW is read if
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* the loop doesn't exist on HW (soldering issue on
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* either signals).
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*/
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<3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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};
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