163 lines
3.4 KiB
Plaintext
163 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/**
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* Device Tree Source for enabling IPC using TI SDK firmware on AM64 SoCs
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*
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* Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&reserved_memory {
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main_r5fss0_core1_dma_memory_region: memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core1_memory_region: memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core0_dma_memory_region: memory@a2000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core0_memory_region: memory@a2100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core1_dma_memory_region: memory@a3000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core1_memory_region: memory@a3100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3100000 0x00 0xf00000>;
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no-map;
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};
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mcu_m4fss_dma_memory_region: memory@a4000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa4000000 0x00 0x100000>;
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no-map;
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};
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mcu_m4fss_memory_region: memory@a4100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa4100000 0x00 0xf00000>;
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no-map;
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};
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rtos_ipc_memory_region: memory@a5000000 {
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reg = <0x00 0xa5000000 0x00 0x00800000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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&mailbox0_cluster2 {
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status = "okay";
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mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
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ti,mbox-rx = <0 0 2>;
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ti,mbox-tx = <1 0 2>;
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};
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mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
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ti,mbox-rx = <2 0 2>;
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ti,mbox-tx = <3 0 2>;
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};
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};
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&mailbox0_cluster4 {
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status = "okay";
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mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
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ti,mbox-rx = <0 0 2>;
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ti,mbox-tx = <1 0 2>;
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};
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mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
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ti,mbox-rx = <2 0 2>;
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ti,mbox-tx = <3 0 2>;
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};
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};
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&mailbox0_cluster6 {
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status = "okay";
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mbox_m4_0: mbox-m4-0 {
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ti,mbox-rx = <0 0 2>;
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ti,mbox-tx = <1 0 2>;
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};
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};
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/* main_timer8 is used by r5f0-0 */
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&main_timer8 {
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status = "reserved";
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};
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/* main_timer9 is used by r5f0-1 */
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&main_timer9 {
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status = "reserved";
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};
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/* main_timer10 is used by r5f1-0 */
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&main_timer10 {
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status = "reserved";
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};
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/* main_timer11 is used by r5f1-1 */
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&main_timer11 {
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status = "reserved";
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};
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&main_r5fss0 {
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status = "okay";
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};
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&main_r5fss0_core0 {
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mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
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memory-region = <&main_r5fss0_core0_dma_memory_region>,
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<&main_r5fss0_core0_memory_region>;
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status = "okay";
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};
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&main_r5fss0_core1 {
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mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
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memory-region = <&main_r5fss0_core1_dma_memory_region>,
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<&main_r5fss0_core1_memory_region>;
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status = "okay";
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};
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&main_r5fss1 {
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status = "okay";
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};
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&main_r5fss1_core0 {
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mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
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memory-region = <&main_r5fss1_core0_dma_memory_region>,
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<&main_r5fss1_core0_memory_region>;
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status = "okay";
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};
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&main_r5fss1_core1 {
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mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
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memory-region = <&main_r5fss1_core1_dma_memory_region>,
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<&main_r5fss1_core1_memory_region>;
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status = "okay";
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};
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&mcu_m4fss {
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mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
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memory-region = <&mcu_m4fss_dma_memory_region>,
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<&mcu_m4fss_memory_region>;
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status = "okay";
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};
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