422 lines
11 KiB
Plaintext
422 lines
11 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
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*/
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#include <dt-bindings/clock/sophgo,cv1800.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "cv18xx-reset.h"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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osc: oscillator {
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compatible = "fixed-clock";
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clock-output-names = "osc_25m";
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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rst: reset-controller@3003000 {
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compatible = "sophgo,cv1800b-reset";
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reg = <0x3003000 0x1000>;
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#reset-cells = <1>;
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};
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mdio: mdio-mux@3009800 {
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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reg = <0x3009800 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio-parent-bus = <&gmac0_mdio>;
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mux-mask = <0x80>;
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status = "disabled";
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internal_mdio: mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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internal_ephy: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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external_mdio: mdio@80 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x80>;
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};
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};
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gpio0: gpio@3020000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x3020000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&rst RST_GPIO0>;
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio1: gpio@3021000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x3021000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&rst RST_GPIO1>;
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portb: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio2: gpio@3022000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x3022000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&rst RST_GPIO2>;
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portc: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio3: gpio@3023000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x3023000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&rst RST_GPIO3>;
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portd: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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saradc: adc@30f0000 {
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compatible = "sophgo,cv1800b-saradc";
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reg = <0x030f0000 0x1000>;
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clocks = <&clk CLK_SARADC>;
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interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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channel@0 {
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reg = <0>;
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};
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channel@1 {
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reg = <1>;
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};
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channel@2 {
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reg = <2>;
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};
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};
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i2c0: i2c@4000000 {
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compatible = "snps,designware-i2c";
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reg = <0x04000000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
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clock-names = "ref", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_I2C0>;
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status = "disabled";
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};
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i2c1: i2c@4010000 {
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compatible = "snps,designware-i2c";
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reg = <0x04010000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
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clock-names = "ref", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_I2C1>;
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status = "disabled";
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};
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i2c2: i2c@4020000 {
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compatible = "snps,designware-i2c";
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reg = <0x04020000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
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clock-names = "ref", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_I2C2>;
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status = "disabled";
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};
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i2c3: i2c@4030000 {
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compatible = "snps,designware-i2c";
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reg = <0x04030000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
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clock-names = "ref", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_I2C3>;
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status = "disabled";
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};
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i2c4: i2c@4040000 {
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compatible = "snps,designware-i2c";
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reg = <0x04040000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
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clock-names = "ref", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_I2C4>;
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status = "disabled";
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};
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gmac0: ethernet@4070000 {
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compatible = "sophgo,cv1800b-dwmac", "snps,dwmac-3.70a";
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reg = <0x04070000 0x10000>;
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clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>;
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clock-names = "stmmaceth", "ptp_ref";
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interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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phy-handle = <&internal_ephy>;
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phy-mode = "internal";
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resets = <&rst RST_ETH0>;
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reset-names = "stmmaceth";
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rx-fifo-depth = <8192>;
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tx-fifo-depth = <8192>;
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snps,multicast-filter-bins = <0>;
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snps,perfect-filter-entries = <1>;
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snps,aal;
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snps,txpbl = <8>;
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snps,rxpbl = <8>;
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snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
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snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
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snps,axi-config = <&gmac0_stmmac_axi_setup>;
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status = "disabled";
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gmac0_mdio: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gmac0_mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <1>;
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queue0 {};
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};
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gmac0_mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <1>;
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queue0 {};
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};
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gmac0_stmmac_axi_setup: stmmac-axi-config {
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snps,blen = <16 8 4 0 0 0 0>;
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snps,rd_osr_lmt = <2>;
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snps,wr_osr_lmt = <1>;
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};
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};
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uart0: serial@4140000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x04140000 0x100>;
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interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst RST_UART0>;
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status = "disabled";
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};
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uart1: serial@4150000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x04150000 0x100>;
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interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst RST_UART1>;
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status = "disabled";
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};
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uart2: serial@4160000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x04160000 0x100>;
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interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst RST_UART2>;
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status = "disabled";
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};
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uart3: serial@4170000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x04170000 0x100>;
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interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst RST_UART3>;
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status = "disabled";
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};
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spi0: spi@4180000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x04180000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
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clock-names = "ssi_clk", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_SPI0>;
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status = "disabled";
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};
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spi1: spi@4190000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x04190000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
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clock-names = "ssi_clk", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_SPI1>;
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status = "disabled";
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};
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spi2: spi@41a0000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x041a0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
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clock-names = "ssi_clk", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_SPI2>;
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status = "disabled";
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};
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spi3: spi@41b0000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x041b0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
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clock-names = "ssi_clk", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_SPI3>;
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status = "disabled";
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};
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uart4: serial@41c0000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x041c0000 0x100>;
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interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst RST_UART4>;
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status = "disabled";
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};
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sdhci0: mmc@4310000 {
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compatible = "sophgo,cv1800b-dwcmshc";
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reg = <0x4310000 0x1000>;
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interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_AXI4_SD0>,
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<&clk CLK_SD0>;
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clock-names = "core", "bus";
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status = "disabled";
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};
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sdhci1: mmc@4320000 {
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compatible = "sophgo,cv1800b-dwcmshc";
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reg = <0x4320000 0x1000>;
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interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_AXI4_SD1>,
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<&clk CLK_SD1>;
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clock-names = "core", "bus";
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status = "disabled";
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};
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dmac: dma-controller@4330000 {
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compatible = "snps,axi-dma-1.01a";
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reg = <0x04330000 0x1000>;
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interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
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clock-names = "core-clk", "cfgr-clk";
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#dma-cells = <1>;
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dma-channels = <8>;
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snps,block-size = <1024 1024 1024 1024
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1024 1024 1024 1024>;
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snps,priority = <0 1 2 3 4 5 6 7>;
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snps,dma-masters = <2>;
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snps,data-width = <2>;
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status = "disabled";
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};
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rtc@5025000 {
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compatible = "sophgo,cv1800b-rtc", "syscon";
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reg = <0x5025000 0x2000>;
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interrupts = <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "alarm", "longpress", "vbat";
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clocks = <&clk CLK_RTC_25M>,
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<&clk CLK_SRC_RTC_SYS_0>;
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clock-names = "rtc", "mcu";
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};
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};
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};
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