243 lines
7.6 KiB
C
243 lines
7.6 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#include "wndw.h"
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#include "atom.h"
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#include <nvif/pushc97b.h>
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#include <nvhw/class/clca7e.h>
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#include <nouveau_bo.h>
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static int
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wndwca7e_image_clr(struct nv50_wndw *wndw)
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{
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struct nvif_push *push = &wndw->wndw.push;
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int ret;
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ret = PUSH_WAIT(push, 4);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7E, SET_PRESENT_CONTROL,
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NVVAL(NVCA7E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, 0) |
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NVDEF(NVCA7E, SET_PRESENT_CONTROL, BEGIN_MODE, NON_TEARING));
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PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_ISO(0),
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NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, ENABLE, DISABLE));
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return 0;
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}
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static int
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wndwca7e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
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{
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const u32 iso0_hi = upper_32_bits(asyw->image.offset[0]);
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const u32 iso0_lo = lower_32_bits(asyw->image.offset[0]);
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struct nvif_push *push = &wndw->wndw.push;
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int ret, kind;
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if (asyw->image.kind)
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kind = NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_BLOCKLINEAR;
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else
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kind = NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_PITCH;
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ret = PUSH_WAIT(push, 17);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_HI_ISO(0), iso0_hi);
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PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_ISO(0),
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NVVAL(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, ADDRESS_LO, iso0_lo >> 4) |
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NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, TARGET, PHYSICAL_NVM) |
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NVVAL(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, KIND, kind) |
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NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, ENABLE, ENABLE));
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PUSH_MTHD(push, NVCA7E, SET_PRESENT_CONTROL,
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NVVAL(NVCA7E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval) |
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NVVAL(NVCA7E, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) |
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NVDEF(NVCA7E, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE));
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PUSH_MTHD(push, NVCA7E, SET_SIZE,
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NVVAL(NVCA7E, SET_SIZE, WIDTH, asyw->image.w) |
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NVVAL(NVCA7E, SET_SIZE, HEIGHT, asyw->image.h),
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SET_STORAGE,
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NVVAL(NVCA7E, SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh),
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SET_PARAMS,
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NVVAL(NVCA7E, SET_PARAMS, FORMAT, asyw->image.format) |
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NVDEF(NVCA7E, SET_PARAMS, CLAMP_BEFORE_BLEND, DISABLE) |
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NVDEF(NVCA7E, SET_PARAMS, SWAP_UV, DISABLE) |
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NVDEF(NVCA7E, SET_PARAMS, FMT_ROUNDING_MODE, ROUND_TO_NEAREST),
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SET_PLANAR_STORAGE(0),
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NVVAL(NVCA7E, SET_PLANAR_STORAGE, PITCH, asyw->image.blocks[0]) |
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NVVAL(NVCA7E, SET_PLANAR_STORAGE, PITCH, asyw->image.pitch[0] >> 6));
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PUSH_MTHD(push, NVCA7E, SET_POINT_IN(0),
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NVVAL(NVCA7E, SET_POINT_IN, X, asyw->state.src_x >> 16) |
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NVVAL(NVCA7E, SET_POINT_IN, Y, asyw->state.src_y >> 16));
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PUSH_MTHD(push, NVCA7E, SET_SIZE_IN,
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NVVAL(NVCA7E, SET_SIZE_IN, WIDTH, asyw->state.src_w >> 16) |
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NVVAL(NVCA7E, SET_SIZE_IN, HEIGHT, asyw->state.src_h >> 16));
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PUSH_MTHD(push, NVCA7E, SET_SIZE_OUT,
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NVVAL(NVCA7E, SET_SIZE_OUT, WIDTH, asyw->state.crtc_w) |
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NVVAL(NVCA7E, SET_SIZE_OUT, HEIGHT, asyw->state.crtc_h));
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return 0;
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}
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static int
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wndwca7e_ilut_clr(struct nv50_wndw *wndw)
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{
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struct nvif_push *push = &wndw->wndw.push;
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int ret;
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ret = PUSH_WAIT(push, 2);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT,
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NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, ENABLE, DISABLE));
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return 0;
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}
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static int
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wndwca7e_ilut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
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{
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const u32 ilut_hi = upper_32_bits(asyw->xlut.i.offset);
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const u32 ilut_lo = lower_32_bits(asyw->xlut.i.offset);
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struct nvif_push *push = &wndw->wndw.push;
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int ret;
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ret = PUSH_WAIT(push, 5);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_HI_ILUT, ilut_hi,
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SET_SURFACE_ADDRESS_LO_ILUT,
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NVVAL(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, ADDRESS_LO, ilut_lo >> 4) |
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NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, TARGET, PHYSICAL_NVM) |
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NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, ENABLE, ENABLE));
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PUSH_MTHD(push, NVCA7E, SET_ILUT_CONTROL,
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NVVAL(NVCA7E, SET_ILUT_CONTROL, SIZE, asyw->xlut.i.size) |
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NVVAL(NVCA7E, SET_ILUT_CONTROL, MODE, asyw->xlut.i.mode) |
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NVVAL(NVCA7E, SET_ILUT_CONTROL, INTERPOLATE, asyw->xlut.i.output_mode));
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return 0;
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}
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static int
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wndwca7e_ntfy_clr(struct nv50_wndw *wndw)
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{
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struct nvif_push *push = &wndw->wndw.push;
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int ret;
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ret = PUSH_WAIT(push, 2);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER,
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NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, ENABLE, DISABLE));
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return 0;
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}
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static int
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wndwca7e_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
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{
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struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
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const u64 ntfy_addr = disp->sync->offset + asyw->ntfy.offset;
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const u32 ntfy_hi = upper_32_bits(ntfy_addr);
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const u32 ntfy_lo = lower_32_bits(ntfy_addr);
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struct nvif_push *push = &wndw->wndw.push;
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int ret;
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ret = PUSH_WAIT(push, 5);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_HI_NOTIFIER, ntfy_hi,
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SET_SURFACE_ADDRESS_LO_NOTIFIER,
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NVVAL(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, ADDRESS_LO, ntfy_lo >> 4) |
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NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, TARGET, PHYSICAL_NVM) |
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NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, ENABLE, ENABLE));
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PUSH_MTHD(push, NVCA7E, SET_NOTIFIER_CONTROL,
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NVVAL(NVCA7E, SET_NOTIFIER_CONTROL, MODE, asyw->ntfy.awaken));
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return 0;
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}
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/****************************************************************
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* Log2(block height) ----------------------------+ *
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* Page Kind ----------------------------------+ | *
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* Gob Height/Page Kind Generation ------+ | | *
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* Sector layout -------+ | | | *
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* Compression ------+ | | | | */
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const u64 wndwca7e_modifiers[] = { /* | | | | | */
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/* 4cpp+ modifiers */
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 0),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 1),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 2),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 3),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 4),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 5),
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/* 1cpp/8bpp modifiers */
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 0),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 1),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 2),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 3),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 4),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 5),
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/* 2cpp/16bpp modifiers */
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 0),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 1),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 2),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 3),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 4),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 5),
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/* All formats support linear */
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DRM_FORMAT_MOD_LINEAR,
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DRM_FORMAT_MOD_INVALID
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};
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static const struct nv50_wndw_func
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wndwca7e = {
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.acquire = wndwc37e_acquire,
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.release = wndwc37e_release,
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.ntfy_set = wndwca7e_ntfy_set,
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.ntfy_clr = wndwca7e_ntfy_clr,
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.ntfy_reset = corec37d_ntfy_init,
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.ntfy_wait_begun = base507c_ntfy_wait_begun,
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.ilut = wndwc57e_ilut,
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.ilut_identity = true,
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.ilut_size = 1024,
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.xlut_set = wndwca7e_ilut_set,
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.xlut_clr = wndwca7e_ilut_clr,
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.csc = base907c_csc,
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.csc_set = wndwc57e_csc_set,
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.csc_clr = wndwc57e_csc_clr,
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.image_set = wndwca7e_image_set,
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.image_clr = wndwca7e_image_clr,
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.blend_set = wndwc37e_blend_set,
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.update = wndwc37e_update,
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};
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int
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wndwca7e_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
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s32 oclass, struct nv50_wndw **pwndw)
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{
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return wndwc37e_new_(&wndwca7e, drm, type, index, oclass, BIT(index >> 1), pwndw);
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}
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