40 lines
855 B
C
40 lines
855 B
C
/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#include "gpu.h"
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#include <engine/fifo/priv.h>
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#include <nvif/class.h>
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const struct nvkm_rm_gpu
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ad10x_gpu = {
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.disp.class = {
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.root = AD102_DISP,
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.caps = GV100_DISP_CAPS,
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.core = AD102_DISP_CORE_CHANNEL_DMA,
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.wndw = GA102_DISP_WINDOW_CHANNEL_DMA,
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.wimm = GA102_DISP_WINDOW_IMM_CHANNEL_DMA,
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.curs = GA102_DISP_CURSOR,
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},
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.usermode.class = AMPERE_USERMODE_A,
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.fifo.chan = {
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.class = AMPERE_CHANNEL_GPFIFO_A,
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.doorbell_handle = tu102_chan_doorbell_handle,
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},
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.ce.class = AMPERE_DMA_COPY_B,
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.gr.class = {
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.i2m = KEPLER_INLINE_TO_MEMORY_B,
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.twod = FERMI_TWOD_A,
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.threed = ADA_A,
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.compute = ADA_COMPUTE_A,
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},
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.nvdec.class = NVC9B0_VIDEO_DECODER,
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.nvenc.class = NVC9B7_VIDEO_ENCODER,
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.ofa.class = NVC9FA_VIDEO_OFA,
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};
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