30 lines
955 B
C
30 lines
955 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2025 Intel Corporation
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*/
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#ifndef _XE_EU_STALL_REGS_H_
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#define _XE_EU_STALL_REGS_H_
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#include "regs/xe_reg_defs.h"
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#define XEHPC_EUSTALL_BASE XE_REG_MCR(0xe520)
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#define XEHPC_EUSTALL_BASE_BUF_ADDR REG_GENMASK(31, 6)
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#define XEHPC_EUSTALL_BASE_XECORE_BUF_SZ REG_GENMASK(5, 3)
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#define XEHPC_EUSTALL_BASE_ENABLE_SAMPLING REG_BIT(1)
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#define XEHPC_EUSTALL_BASE_UPPER XE_REG_MCR(0xe524)
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#define XEHPC_EUSTALL_REPORT XE_REG_MCR(0xe528, XE_REG_OPTION_MASKED)
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#define XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK REG_GENMASK(15, 2)
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#define XEHPC_EUSTALL_REPORT_OVERFLOW_DROP REG_BIT(1)
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#define XEHPC_EUSTALL_REPORT1 XE_REG_MCR(0xe52c, XE_REG_OPTION_MASKED)
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#define XEHPC_EUSTALL_REPORT1_READ_PTR_MASK REG_GENMASK(15, 2)
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#define XEHPC_EUSTALL_CTRL XE_REG_MCR(0xe53c, XE_REG_OPTION_MASKED)
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#define EUSTALL_MOCS REG_GENMASK(9, 3)
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#define EUSTALL_SAMPLE_RATE REG_GENMASK(2, 0)
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#endif
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