75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
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* Copyright (c) 2014, Synopsys, Inc.
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* All rights reserved
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*
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* Author: Raju Rangoju <Raju.Rangoju@amd.com>
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*/
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#include "xgbe.h"
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#include "xgbe-common.h"
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static u32 get_pps_mask(unsigned int x)
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{
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return GENMASK(PPS_MAXIDX(x), PPS_MINIDX(x));
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}
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static u32 get_pps_cmd(unsigned int x, u32 val)
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{
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return (val & GENMASK(3, 0)) << PPS_MINIDX(x);
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}
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static u32 get_target_mode_sel(unsigned int x, u32 val)
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{
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return (val & GENMASK(1, 0)) << (PPS_MAXIDX(x) - 2);
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}
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int xgbe_pps_config(struct xgbe_prv_data *pdata,
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struct xgbe_pps_config *cfg, int index, bool on)
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{
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unsigned int ppscr = 0;
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unsigned int tnsec;
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u64 period;
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/* Check if target time register is busy */
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tnsec = XGMAC_IOREAD(pdata, MAC_PPSx_TTNSR(index));
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if (XGMAC_GET_BITS(tnsec, MAC_PPSx_TTNSR, TRGTBUSY0))
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return -EBUSY;
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ppscr = XGMAC_IOREAD(pdata, MAC_PPSCR);
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ppscr &= ~get_pps_mask(index);
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if (!on) {
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/* Disable PPS output */
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ppscr |= get_pps_cmd(index, XGBE_PPSCMD_STOP);
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ppscr |= PPSEN0;
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XGMAC_IOWRITE(pdata, MAC_PPSCR, ppscr);
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return 0;
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}
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/* Configure start time */
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XGMAC_IOWRITE(pdata, MAC_PPSx_TTSR(index), cfg->start.tv_sec);
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XGMAC_IOWRITE(pdata, MAC_PPSx_TTNSR(index), cfg->start.tv_nsec);
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period = cfg->period.tv_sec * NSEC_PER_SEC + cfg->period.tv_nsec;
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period = div_u64(period, XGBE_V2_TSTAMP_SSINC);
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if (period < 4)
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return -EINVAL;
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/* Configure interval and pulse width (50% duty cycle) */
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XGMAC_IOWRITE(pdata, MAC_PPSx_INTERVAL(index), period - 1);
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XGMAC_IOWRITE(pdata, MAC_PPSx_WIDTH(index), (period >> 1) - 1);
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/* Enable PPS with pulse train mode */
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ppscr |= get_pps_cmd(index, XGBE_PPSCMD_START);
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ppscr |= get_target_mode_sel(index, XGBE_PPSTARGET_PULSE);
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ppscr |= PPSEN0;
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XGMAC_IOWRITE(pdata, MAC_PPSCR, ppscr);
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return 0;
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}
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