148 lines
3.7 KiB
C
148 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/G3E System controller (SYS) driver
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include "rz-sysc.h"
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/* Register Offsets */
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#define SYS_LSI_MODE 0x300
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/*
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* BOOTPLLCA[1:0]
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* [0,0] => 1.1GHZ
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* [0,1] => 1.5GHZ
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* [1,0] => 1.6GHZ
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* [1,1] => 1.7GHZ
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*/
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#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)
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#define SYS_LSI_MODE_CA55_1_7GHZ 0x3
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#define SYS_LSI_PRR 0x308
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#define SYS_LSI_PRR_CA55_DIS BIT(8)
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#define SYS_LSI_PRR_NPU_DIS BIT(1)
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#define SYS_LSI_OTPTSU1TRMVAL0 0x330
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#define SYS_LSI_OTPTSU1TRMVAL1 0x334
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#define SYS_SPI_STAADDCS0 0x900
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#define SYS_SPI_ENDADDCS0 0x904
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#define SYS_SPI_STAADDCS1 0x908
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#define SYS_SPI_ENDADDCS1 0x90c
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#define SYS_VSP_CLK 0xe00
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#define SYS_GBETH0_CFG 0xf00
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#define SYS_GBETH1_CFG 0xf04
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#define SYS_PCIE_INTX_CH0 0x1000
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#define SYS_PCIE_MSI1_CH0 0x1004
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#define SYS_PCIE_MSI2_CH0 0x1008
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#define SYS_PCIE_MSI3_CH0 0x100c
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#define SYS_PCIE_MSI4_CH0 0x1010
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#define SYS_PCIE_MSI5_CH0 0x1014
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#define SYS_PCIE_PME_CH0 0x1018
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#define SYS_PCIE_ACK_CH0 0x101c
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#define SYS_PCIE_MISC_CH0 0x1020
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#define SYS_PCIE_MODE_CH0 0x1024
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#define SYS_ADC_CFG 0x1600
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static void rzg3e_sys_print_id(struct device *dev,
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void __iomem *sysc_base,
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struct soc_device_attribute *soc_dev_attr)
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{
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bool is_quad_core, npu_enabled;
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u32 prr_val, mode_val;
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prr_val = readl(sysc_base + SYS_LSI_PRR);
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mode_val = readl(sysc_base + SYS_LSI_MODE);
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/* Check CPU and NPU configuration */
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is_quad_core = !(prr_val & SYS_LSI_PRR_CA55_DIS);
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npu_enabled = !(prr_val & SYS_LSI_PRR_NPU_DIS);
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dev_info(dev, "Detected Renesas %s Core %s %s Rev %s%s\n",
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is_quad_core ? "Quad" : "Dual", soc_dev_attr->family,
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soc_dev_attr->soc_id, soc_dev_attr->revision,
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npu_enabled ? " with Ethos-U55" : "");
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/* Check CA55 PLL configuration */
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if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
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dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
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}
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static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initconst = {
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.family = "RZ/G3E",
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.id = 0x8679447,
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.devid_offset = 0x304,
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.revision_mask = GENMASK(31, 28),
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.specific_id_mask = GENMASK(27, 0),
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.print_id = rzg3e_sys_print_id,
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};
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static bool rzg3e_regmap_readable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case SYS_LSI_OTPTSU1TRMVAL0:
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case SYS_LSI_OTPTSU1TRMVAL1:
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case SYS_SPI_STAADDCS0:
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case SYS_SPI_ENDADDCS0:
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case SYS_SPI_STAADDCS1:
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case SYS_SPI_ENDADDCS1:
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case SYS_VSP_CLK:
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case SYS_GBETH0_CFG:
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case SYS_GBETH1_CFG:
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case SYS_PCIE_INTX_CH0:
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case SYS_PCIE_MSI1_CH0:
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case SYS_PCIE_MSI2_CH0:
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case SYS_PCIE_MSI3_CH0:
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case SYS_PCIE_MSI4_CH0:
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case SYS_PCIE_MSI5_CH0:
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case SYS_PCIE_PME_CH0:
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case SYS_PCIE_ACK_CH0:
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case SYS_PCIE_MISC_CH0:
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case SYS_PCIE_MODE_CH0:
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case SYS_ADC_CFG:
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return true;
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default:
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return false;
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}
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}
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static bool rzg3e_regmap_writeable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case SYS_SPI_STAADDCS0:
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case SYS_SPI_ENDADDCS0:
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case SYS_SPI_STAADDCS1:
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case SYS_SPI_ENDADDCS1:
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case SYS_VSP_CLK:
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case SYS_GBETH0_CFG:
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case SYS_GBETH1_CFG:
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case SYS_PCIE_INTX_CH0:
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case SYS_PCIE_MSI1_CH0:
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case SYS_PCIE_MSI2_CH0:
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case SYS_PCIE_MSI3_CH0:
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case SYS_PCIE_MSI4_CH0:
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case SYS_PCIE_MSI5_CH0:
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case SYS_PCIE_PME_CH0:
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case SYS_PCIE_ACK_CH0:
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case SYS_PCIE_MISC_CH0:
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case SYS_PCIE_MODE_CH0:
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case SYS_ADC_CFG:
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return true;
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default:
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return false;
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}
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}
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const struct rz_sysc_init_data rzg3e_sys_init_data = {
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.soc_id_init_data = &rzg3e_sys_soc_id_init_data,
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.readable_reg = rzg3e_regmap_readable_reg,
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.writeable_reg = rzg3e_regmap_writeable_reg,
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.max_register = 0x170c,
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};
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