184 lines
3.8 KiB
C
184 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd
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* Copyright (c) 2025 Kaustabh Chakraborty <kauschluss@disroot.org>
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*/
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#ifndef __LINUX_MFD_S2MPU05_H
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#define __LINUX_MFD_S2MPU05_H
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/* S2MPU05 registers */
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enum S2MPU05_reg {
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S2MPU05_REG_ID,
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S2MPU05_REG_INT1,
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S2MPU05_REG_INT2,
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S2MPU05_REG_INT3,
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S2MPU05_REG_INT1M,
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S2MPU05_REG_INT2M,
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S2MPU05_REG_INT3M,
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S2MPU05_REG_ST1,
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S2MPU05_REG_ST2,
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S2MPU05_REG_PWRONSRC,
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S2MPU05_REG_OFFSRC,
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S2MPU05_REG_BU_CHG,
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S2MPU05_REG_RTC_BUF,
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S2MPU05_REG_CTRL1,
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S2MPU05_REG_CTRL2,
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S2MPU05_REG_ETC_TEST,
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S2MPU05_REG_OTP_ADRL,
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S2MPU05_REG_OTP_ADRH,
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S2MPU05_REG_OTP_DATA,
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S2MPU05_REG_MON1SEL,
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S2MPU05_REG_MON2SEL,
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S2MPU05_REG_CTRL3,
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S2MPU05_REG_ETC_OTP,
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S2MPU05_REG_UVLO,
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S2MPU05_REG_TIME_CTRL1,
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S2MPU05_REG_TIME_CTRL2,
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S2MPU05_REG_B1CTRL1,
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S2MPU05_REG_B1CTRL2,
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S2MPU05_REG_B2CTRL1,
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S2MPU05_REG_B2CTRL2,
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S2MPU05_REG_B2CTRL3,
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S2MPU05_REG_B2CTRL4,
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S2MPU05_REG_B3CTRL1,
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S2MPU05_REG_B3CTRL2,
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S2MPU05_REG_B3CTRL3,
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S2MPU05_REG_B4CTRL1,
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S2MPU05_REG_B4CTRL2,
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S2MPU05_REG_B5CTRL1,
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S2MPU05_REG_B5CTRL2,
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S2MPU05_REG_BUCK_RAMP,
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S2MPU05_REG_LDO_DVS1,
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S2MPU05_REG_LDO_DVS9,
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S2MPU05_REG_LDO_DVS10,
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S2MPU05_REG_L1CTRL,
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S2MPU05_REG_L2CTRL,
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S2MPU05_REG_L3CTRL,
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S2MPU05_REG_L4CTRL,
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S2MPU05_REG_L5CTRL,
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S2MPU05_REG_L6CTRL,
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S2MPU05_REG_L7CTRL,
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S2MPU05_REG_L8CTRL,
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S2MPU05_REG_L9CTRL1,
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S2MPU05_REG_L9CTRL2,
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S2MPU05_REG_L10CTRL,
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S2MPU05_REG_L11CTRL1,
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S2MPU05_REG_L11CTRL2,
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S2MPU05_REG_L12CTRL,
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S2MPU05_REG_L13CTRL,
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S2MPU05_REG_L14CTRL,
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S2MPU05_REG_L15CTRL,
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S2MPU05_REG_L16CTRL,
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S2MPU05_REG_L17CTRL1,
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S2MPU05_REG_L17CTRL2,
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S2MPU05_REG_L18CTRL1,
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S2MPU05_REG_L18CTRL2,
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S2MPU05_REG_L19CTRL,
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S2MPU05_REG_L20CTRL,
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S2MPU05_REG_L21CTRL,
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S2MPU05_REG_L22CTRL,
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S2MPU05_REG_L23CTRL,
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S2MPU05_REG_L24CTRL,
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S2MPU05_REG_L25CTRL,
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S2MPU05_REG_L26CTRL,
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S2MPU05_REG_L27CTRL,
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S2MPU05_REG_L28CTRL,
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S2MPU05_REG_L29CTRL,
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S2MPU05_REG_L30CTRL,
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S2MPU05_REG_L31CTRL,
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S2MPU05_REG_L32CTRL,
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S2MPU05_REG_L33CTRL,
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S2MPU05_REG_L34CTRL,
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S2MPU05_REG_L35CTRL,
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S2MPU05_REG_LDO_DSCH1,
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S2MPU05_REG_LDO_DSCH2,
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S2MPU05_REG_LDO_DSCH3,
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S2MPU05_REG_LDO_DSCH4,
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S2MPU05_REG_LDO_DSCH5,
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S2MPU05_REG_LDO_CTRL1,
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S2MPU05_REG_LDO_CTRL2,
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S2MPU05_REG_TCXO_CTRL,
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S2MPU05_REG_SELMIF,
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};
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/* S2MPU05 regulator ids */
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enum S2MPU05_regulators {
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S2MPU05_LDO1,
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S2MPU05_LDO2,
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S2MPU05_LDO3,
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S2MPU05_LDO4,
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S2MPU05_LDO5,
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S2MPU05_LDO6,
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S2MPU05_LDO7,
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S2MPU05_LDO8,
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S2MPU05_LDO9,
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S2MPU05_LDO10,
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S2MPU05_LDO11,
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S2MPU05_LDO12,
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S2MPU05_LDO13,
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S2MPU05_LDO14,
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S2MPU05_LDO15,
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S2MPU05_LDO16,
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S2MPU05_LDO17,
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S2MPU05_LDO18,
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S2MPU05_LDO19,
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S2MPU05_LDO20,
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S2MPU05_LDO21,
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S2MPU05_LDO22,
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S2MPU05_LDO23,
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S2MPU05_LDO24,
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S2MPU05_LDO25,
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S2MPU05_LDO26,
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S2MPU05_LDO27,
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S2MPU05_LDO28,
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S2MPU05_LDO29,
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S2MPU05_LDO30,
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S2MPU05_LDO31,
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S2MPU05_LDO32,
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S2MPU05_LDO33,
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S2MPU05_LDO34,
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S2MPU05_LDO35,
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S2MPU05_BUCK1,
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S2MPU05_BUCK2,
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S2MPU05_BUCK3,
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S2MPU05_BUCK4,
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S2MPU05_BUCK5,
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S2MPU05_REGULATOR_MAX,
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};
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#define S2MPU05_SW_ENABLE_MASK 0x03
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#define S2MPU05_ENABLE_TIME_LDO 128
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#define S2MPU05_ENABLE_TIME_BUCK1 110
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#define S2MPU05_ENABLE_TIME_BUCK2 110
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#define S2MPU05_ENABLE_TIME_BUCK3 110
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#define S2MPU05_ENABLE_TIME_BUCK4 150
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#define S2MPU05_ENABLE_TIME_BUCK5 150
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#define S2MPU05_LDO_MIN1 800000
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#define S2MPU05_LDO_MIN2 1800000
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#define S2MPU05_LDO_MIN3 400000
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#define S2MPU05_LDO_STEP1 12500
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#define S2MPU05_LDO_STEP2 25000
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#define S2MPU05_BUCK_MIN1 400000
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#define S2MPU05_BUCK_MIN2 600000
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#define S2MPU05_BUCK_STEP1 6250
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#define S2MPU05_BUCK_STEP2 12500
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#define S2MPU05_RAMP_DELAY 12000 /* uV/uS */
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#define S2MPU05_ENABLE_SHIFT 6
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#define S2MPU05_ENABLE_MASK (0x03 << S2MPU05_ENABLE_SHIFT)
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#define S2MPU05_LDO_VSEL_MASK 0x3F
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#define S2MPU05_BUCK_VSEL_MASK 0xFF
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#define S2MPU05_LDO_N_VOLTAGES (S2MPU05_LDO_VSEL_MASK + 1)
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#define S2MPU05_BUCK_N_VOLTAGES (S2MPU05_BUCK_VSEL_MASK + 1)
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#define S2MPU05_PMIC_EN_SHIFT 6
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#endif /* __LINUX_MFD_S2MPU05_H */
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