147 lines
3.6 KiB
Plaintext
147 lines
3.6 KiB
Plaintext
Marvell Armada AP80x System Controller
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======================================
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The AP806/AP807 is one of the two core HW blocks of the Marvell Armada
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7K/8K/931x SoCs. It contains system controllers, which provide several
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registers giving access to numerous features: clocks, pin-muxing and
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many other SoC configuration items. This DT binding allows to describe
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these system controllers.
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For the top level node:
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- compatible: must be: "syscon", "simple-mfd";
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- reg: register area of the AP80x system controller
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SYSTEM CONTROLLER 0
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===================
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Clocks:
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-------
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The Device Tree node representing the AP806/AP807 system controller
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provides a number of clocks:
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- 0: reference clock of CPU cluster 0
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- 1: reference clock of CPU cluster 1
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- 2: fixed PLL at 1200 Mhz
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- 3: MSS clock, derived from the fixed PLL
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Required properties:
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- compatible: must be one of:
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* "marvell,ap806-clock"
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* "marvell,ap807-clock"
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- #clock-cells: must be set to 1
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Pinctrl:
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--------
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For common binding part and usage, refer to
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Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
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Required properties:
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- compatible must be "marvell,ap806-pinctrl",
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Available mpp pins/groups and functions:
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Note: brackets (x) are not part of the mpp name for marvell,function and given
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only for more detailed description in this document.
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name pins functions
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================================================================================
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mpp0 0 gpio, sdio(clk), spi0(clk)
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mpp1 1 gpio, sdio(cmd), spi0(miso)
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mpp2 2 gpio, sdio(d0), spi0(mosi)
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mpp3 3 gpio, sdio(d1), spi0(cs0n)
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mpp4 4 gpio, sdio(d2), i2c0(sda)
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mpp5 5 gpio, sdio(d3), i2c0(sdk)
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mpp6 6 gpio, sdio(ds)
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mpp7 7 gpio, sdio(d4), uart1(rxd)
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mpp8 8 gpio, sdio(d5), uart1(txd)
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mpp9 9 gpio, sdio(d6), spi0(cs1n)
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mpp10 10 gpio, sdio(d7)
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mpp11 11 gpio, uart0(txd)
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mpp12 12 gpio, sdio(pw_off), sdio(hw_rst)
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mpp13 13 gpio
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mpp14 14 gpio
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mpp15 15 gpio
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mpp16 16 gpio
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mpp17 17 gpio
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mpp18 18 gpio
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mpp19 19 gpio, uart0(rxd), sdio(pw_off)
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GPIO:
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-----
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For common binding part and usage, refer to
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Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.
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Required properties:
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- compatible: "marvell,armada-8k-gpio"
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- offset: offset address inside the syscon block
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Optional properties:
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- marvell,pwm-offset: offset address of PWM duration control registers inside
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the syscon block
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Example:
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ap_syscon: system-controller@6f4000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x6f4000 0x1000>;
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ap_clk: clock {
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compatible = "marvell,ap806-clock";
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#clock-cells = <1>;
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};
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ap_pinctrl: pinctrl {
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compatible = "marvell,ap806-pinctrl";
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};
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ap_gpio: gpio {
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compatible = "marvell,armada-8k-gpio";
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offset = <0x1040>;
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ngpios = <19>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&ap_pinctrl 0 0 19>;
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marvell,pwm-offset = <0x10c0>;
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#pwm-cells = <2>;
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clocks = <&ap_clk 3>;
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};
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};
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SYSTEM CONTROLLER 1
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===================
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Cluster clocks:
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---------------
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Device Tree Clock bindings for cluster clock of Marvell
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AP806/AP807. Each cluster contain up to 2 CPUs running at the same
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frequency.
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Required properties:
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- compatible: must be one of:
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* "marvell,ap806-cpu-clock"
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* "marvell,ap807-cpu-clock"
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- #clock-cells : should be set to 1.
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- clocks : shall be the input parent clock(s) phandle for the clock
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(one per cluster)
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- reg: register range associated with the cluster clocks
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ap_syscon1: system-controller@6f8000 {
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compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
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reg = <0x6f8000 0x1000>;
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cpu_clk: clock-cpu@278 {
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compatible = "marvell,ap806-cpu-clock";
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clocks = <&ap_clk 0>, <&ap_clk 1>;
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#clock-cells = <1>;
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reg = <0x278 0xa30>;
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};
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};
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