52 lines
1.1 KiB
YAML
52 lines
1.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/marvell,berlin2-clk.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Berlin Clock Controller
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maintainers:
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- Jisheng Zhang <jszhang@kernel.org>
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description:
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Clock related registers are spread among the chip control registers. Berlin
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clock node should be a sub-node of the chip controller node. Marvell Berlin2
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(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some minor
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differences in features and register layout.
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properties:
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compatible:
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enum:
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- marvell,berlin2-clk
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- marvell,berlin2q-clk
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'#clock-cells':
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const: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- enum:
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- refclk
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- video_ext0
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required:
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- compatible
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- '#clock-cells'
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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clock-controller {
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compatible = "marvell,berlin2q-clk";
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#clock-cells = <1>;
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clocks = <&refclk>;
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clock-names = "refclk";
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};
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