56 lines
1.5 KiB
YAML
56 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller on QCS615
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maintainers:
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm display clock control module provides the clocks, resets and power
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domains on QCS615.
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See also: include/dt-bindings/clock/qcom,qcs615-dispcc.h
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properties:
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compatible:
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const: qcom,qcs615-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 clock source from GCC
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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- description: Pixel clock from DSI PHY1
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- description: Display port PLL link clock
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- description: Display port PLL VCO DIV clock
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,qcs615-gcc.h>
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clock-controller@af00000 {
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compatible = "qcom,qcs615-dispcc";
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reg = <0x0af00000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
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<&mdss_dsi0_phy 0>,
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<&mdss_dsi0_phy 1>,
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<&mdss_dsi1_phy 0>,
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<&mdss_dp_phy 0>,
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<&mdss_dp_vco 0>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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