194 lines
4.9 KiB
YAML
194 lines
4.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ldb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale LVDS Display Bridge (ldb)
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description:
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The LVDS Display Bridge device tree node contains up to two lvds-channel
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nodes describing each of the two LVDS encoder channels of the bridge.
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,imx53-ldb
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- items:
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- enum:
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- fsl,imx6q-ldb
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- const: fsl,imx53-ldb
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reg:
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maxItems: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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gpr:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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The phandle points to the iomuxc-gpr region containing the LVDS
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control register.
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clocks:
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minItems: 6
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maxItems: 8
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clock-names:
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oneOf:
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- items:
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- const: di0_pll
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- const: di1_pll
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- const: di0_sel
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- const: di1_sel
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- const: di0
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- const: di1
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- items:
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- const: di0_pll
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- const: di1_pll
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- const: di0_sel
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- const: di1_sel
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- const: di2_sel
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- const: di3_sel
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- const: di0
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- const: di1
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fsl,dual-channel:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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if it exists, only LVDS channel 0 should
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be configured - one input will be distributed on both outputs in dual
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channel mode
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patternProperties:
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'^lvds-channel@[0-1]$':
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type: object
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description:
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Each LVDS Channel has to contain either an of graph link to a panel device node
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or a display-timings node that describes the video timings for the connected
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LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
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properties:
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reg:
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maxItems: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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display-timings:
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$ref: /schemas/display/panel/display-timings.yaml#
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fsl,data-mapping:
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enum:
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- spwg
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- jeida
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fsl,data-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: should be <18> or <24>
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enum:
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- 18
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- 24
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fsl,panel:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to lcd panel
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patternProperties:
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'^port@[0-4]$':
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$ref: /schemas/graph.yaml#/properties/port
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description:
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On i.MX5, the internal two-input-multiplexer is used. Due to hardware
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limitations, only one input port (port@[0,1]) can be used for each channel
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(lvds-channel@[0,1], respectively).
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On i.MX6, there should be four input ports (port@[0-3]) that correspond
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to the four LVDS multiplexer inputs.
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A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
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to a panel input port. Optionally, the output port can be left out if
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display-timings are used instead.
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additionalProperties: false
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required:
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- compatible
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- gpr
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx5-clock.h>
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ldb@53fa8008 {
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compatible = "fsl,imx53-ldb";
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reg = <0x53fa8008 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpr = <&gpr>;
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clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
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<&clks IMX5_CLK_LDB_DI1_SEL>,
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<&clks IMX5_CLK_IPU_DI0_SEL>,
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<&clks IMX5_CLK_IPU_DI1_SEL>,
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<&clks IMX5_CLK_LDB_DI0_GATE>,
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<&clks IMX5_CLK_LDB_DI1_GATE>;
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clock-names = "di0_pll", "di1_pll",
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"di0_sel", "di1_sel",
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"di0", "di1";
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/* Using an of-graph endpoint link to connect the panel */
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lvds-channel@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&ipu_di0_lvds0>;
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};
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};
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port@2 {
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reg = <2>;
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endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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/* Using display-timings and fsl,data-mapping/width instead */
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lvds-channel@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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fsl,data-mapping = "spwg";
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fsl,data-width = <24>;
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display-timings {/* ... */
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};
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port@1 {
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reg = <1>;
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endpoint {
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remote-endpoint = <&ipu_di1_lvds1>;
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};
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};
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};
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};
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