69 lines
1.7 KiB
YAML
69 lines
1.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/atmel,at91sam9g45-dma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Atmel Direct Memory Access Controller (DMA)
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maintainers:
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- Ludovic Desroches <ludovic.desroches@microchip.com>
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description:
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The Atmel Direct Memory Access Controller (DMAC) transfers data from a source
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peripheral to a destination peripheral over one or more AMBA buses. One channel
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is required for each source/destination pair. In the most basic configuration,
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the DMAC has one master interface and one channel. The master interface reads
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the data from a source and writes it to a destination. Two AMBA transfers are
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required for each DMAC data transfer. This is also known as a dual-access transfer.
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The DMAC is programmed via the APB interface.
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properties:
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compatible:
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enum:
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- atmel,at91sam9g45-dma
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- atmel,at91sam9rl-dma
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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"#dma-cells":
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description:
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Must be <2>, used to represent the number of integer cells in the dma
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property of client devices. The two cells in order are
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1. The first cell represents the channel number.
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2. The second cell is 0 for RX and 1 for TX transfers.
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const: 2
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clocks:
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maxItems: 1
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clock-names:
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const: dma_clk
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required:
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- compatible
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- reg
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- interrupts
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- "#dma-cells"
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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dma-controller@ffffec00 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffec00 0x200>;
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interrupts = <21>;
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#dma-cells = <2>;
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clocks = <&pmc 2 20>;
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clock-names = "dma_clk";
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};
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...
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