83 lines
2.2 KiB
YAML
83 lines
2.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/atmel,sama5d4-dma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip AT91 Extensible Direct Memory Access Controller
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maintainers:
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- Nicolas Ferre <nicolas.ferre@microchip.com>
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- Charan Pedumuru <charan.pedumuru@microchip.com>
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description:
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The DMA Controller (XDMAC) is a AHB-protocol central direct memory access
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controller. It performs peripheral data transfer and memory move operations
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over one or two bus ports through the unidirectional communication
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channel. Each channel is fully programmable and provides both peripheral
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or memory-to-memory transfers. The channel features are configurable at
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implementation.
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allOf:
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- $ref: dma-controller.yaml#
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properties:
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compatible:
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oneOf:
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- enum:
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- atmel,sama5d4-dma
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- microchip,sama7g5-dma
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- items:
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- enum:
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- microchip,sam9x60-dma
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- microchip,sam9x7-dma
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- const: atmel,sama5d4-dma
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- items:
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- const: microchip,sama7d65-dma
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- const: microchip,sama7g5-dma
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"#dma-cells":
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description: |
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Represents the number of integer cells in the `dmas` property of client
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devices. The single cell specifies the channel configuration register:
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- bit 13: SIF (Source Interface Identifier) for memory interface.
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- bit 14: DIF (Destination Interface Identifier) for peripheral interface.
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- bit 30-24: PERID (Peripheral Identifier).
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const: 1
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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const: dma_clk
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- "#dma-cells"
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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dma-controller@f0008000 {
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compatible = "atmel,sama5d4-dma";
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reg = <0xf0008000 0x1000>;
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interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <1>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
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clock-names = "dma_clk";
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};
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