73 lines
1.7 KiB
YAML
73 lines
1.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/i3c/adi,i3c-master.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Analog Devices I3C Controller
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description:
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FPGA-based I3C controller designed to interface with I3C and I2C peripherals,
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implementing a subset of the I3C-basic specification. The IP core is tested
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on arm, microblaze, and arm64 architectures.
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https://analogdevicesinc.github.io/hdl/library/i3c_controller
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maintainers:
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- Jorge Marques <jorge.marques@analog.com>
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properties:
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compatible:
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const: adi,i3c-master-v1
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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items:
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- description: The AXI interconnect clock, drives the register map.
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- description:
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The secondary clock, drives the internal logic asynchronously to the
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register map. The presence of this entry states that the IP Core was
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synthesized with a second clock input, and the absence of this entry
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indicates a topology where a single clock input drives all the
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internal logic.
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clock-names:
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minItems: 1
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items:
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- const: axi
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- const: i3c
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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allOf:
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- $ref: i3c.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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i3c@44a00000 {
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compatible = "adi,i3c-master-v1";
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reg = <0x44a00000 0x1000>;
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interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc 15>, <&clkc 15>;
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clock-names = "axi", "i3c";
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#address-cells = <3>;
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#size-cells = <0>;
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/* I3C and I2C devices */
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};
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