268 lines
6.8 KiB
YAML
268 lines
6.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Generic Interrupt Controller, version 5
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maintainers:
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- Lorenzo Pieralisi <lpieralisi@kernel.org>
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- Marc Zyngier <maz@kernel.org>
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description: |
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The GICv5 architecture defines the guidelines to implement GICv5
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compliant interrupt controllers for AArch64 systems.
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The GICv5 specification can be found at
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https://developer.arm.com/documentation/aes0070
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The GICv5 architecture is composed of multiple components:
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- one or more IRS (Interrupt Routing Service)
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- zero or more ITS (Interrupt Translation Service)
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The architecture defines:
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- PE-Private Peripheral Interrupts (PPI)
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- Shared Peripheral Interrupts (SPI)
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- Logical Peripheral Interrupts (LPI)
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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properties:
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compatible:
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const: arm,gic-v5
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"#address-cells":
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enum: [ 1, 2 ]
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"#size-cells":
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enum: [ 1, 2 ]
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ranges: true
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"#interrupt-cells":
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description: |
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The 1st cell corresponds to the INTID.Type field in the INTID; 1 for PPI,
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3 for SPI. LPI interrupts must not be described in the bindings since
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they are allocated dynamically by the software component managing them.
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The 2nd cell contains the interrupt INTID.ID field.
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The 3rd cell is the flags, encoded as follows:
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bits[3:0] trigger type and level flags.
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1 = low-to-high edge triggered
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2 = high-to-low edge triggered
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4 = active high level-sensitive
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8 = active low level-sensitive
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const: 3
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interrupt-controller: true
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interrupts:
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description:
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The VGIC maintenance interrupt.
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maxItems: 1
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required:
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- compatible
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- "#address-cells"
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- "#size-cells"
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- ranges
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- "#interrupt-cells"
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- interrupt-controller
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patternProperties:
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"^irs@[0-9a-f]+$":
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type: object
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description:
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GICv5 has one or more Interrupt Routing Services (IRS) that are
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responsible for handling IRQ state and routing.
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additionalProperties: false
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properties:
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compatible:
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const: arm,gic-v5-irs
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reg:
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minItems: 1
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items:
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- description: IRS config frames
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- description: IRS setlpi frames
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reg-names:
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description:
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Describe config and setlpi frames that are present.
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"ns-" stands for non-secure, "s-" for secure, "realm-" for realm
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and "el3-" for EL3.
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minItems: 1
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maxItems: 8
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items:
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enum: [ ns-config, s-config, realm-config, el3-config, ns-setlpi,
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s-setlpi, realm-setlpi, el3-setlpi ]
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"#address-cells":
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enum: [ 1, 2 ]
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"#size-cells":
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enum: [ 1, 2 ]
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ranges: true
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dma-noncoherent:
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description:
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Present if the GIC IRS permits programming shareability and
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cacheability attributes but is connected to a non-coherent
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downstream interconnect.
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cpus:
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description:
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CPUs managed by the IRS.
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arm,iaffids:
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$ref: /schemas/types.yaml#/definitions/uint16-array
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description:
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Interrupt AFFinity ID (IAFFID) associated with the CPU whose
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CPU node phandle is at the same index in the cpus array.
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patternProperties:
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"^its@[0-9a-f]+$":
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type: object
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description:
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GICv5 has zero or more Interrupt Translation Services (ITS) that are
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used to route Message Signalled Interrupts (MSI) to the CPUs. Each
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ITS is connected to an IRS.
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additionalProperties: false
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properties:
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compatible:
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const: arm,gic-v5-its
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reg:
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items:
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- description: ITS config frames
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reg-names:
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description:
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Describe config frames that are present.
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"ns-" stands for non-secure, "s-" for secure, "realm-" for realm
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and "el3-" for EL3.
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minItems: 1
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maxItems: 4
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items:
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enum: [ ns-config, s-config, realm-config, el3-config ]
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"#address-cells":
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enum: [ 1, 2 ]
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"#size-cells":
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enum: [ 1, 2 ]
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ranges: true
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dma-noncoherent:
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description:
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Present if the GIC ITS permits programming shareability and
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cacheability attributes but is connected to a non-coherent
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downstream interconnect.
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patternProperties:
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"^msi-controller@[0-9a-f]+$":
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type: object
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description:
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GICv5 ITS has one or more translate register frames.
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additionalProperties: false
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properties:
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reg:
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items:
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- description: ITS translate frames
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reg-names:
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description:
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Describe translate frames that are present.
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"ns-" stands for non-secure, "s-" for secure, "realm-" for realm
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and "el3-" for EL3.
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minItems: 1
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maxItems: 4
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items:
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enum: [ ns-translate, s-translate, realm-translate, el3-translate ]
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"#msi-cells":
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description:
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The single msi-cell is the DeviceID of the device which will
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generate the MSI.
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const: 1
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msi-controller: true
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required:
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- reg
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- reg-names
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- "#msi-cells"
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- msi-controller
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required:
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- compatible
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- reg
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- reg-names
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required:
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- compatible
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- reg
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- reg-names
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- cpus
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- arm,iaffids
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additionalProperties: false
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examples:
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- |
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interrupt-controller {
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compatible = "arm,gic-v5";
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#interrupt-cells = <3>;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <1 25 4>;
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irs@2f1a0000 {
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compatible = "arm,gic-v5-irs";
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reg = <0x2f1a0000 0x10000>; // IRS_CONFIG_FRAME
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reg-names = "ns-config";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
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arm,iaffids = /bits/ 16 <0 1 2 3 4 5 6 7>;
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its@2f120000 {
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compatible = "arm,gic-v5-its";
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reg = <0x2f120000 0x10000>; // ITS_CONFIG_FRAME
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reg-names = "ns-config";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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msi-controller@2f130000 {
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reg = <0x2f130000 0x10000>; // ITS_TRANSLATE_FRAME
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reg-names = "ns-translate";
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#msi-cells = <1>;
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msi-controller;
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};
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};
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};
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};
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...
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