82 lines
2.1 KiB
YAML
82 lines
2.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm6345-l1-intc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom BCM6345-style Level 1 interrupt controller
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maintainers:
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- Simon Arlott <simon@octiron.net>
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description: >
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This block is a first level interrupt controller that is typically connected
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directly to one of the HW INT lines on each CPU.
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Key elements of the hardware design include:
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- 32, 64 or 128 incoming level IRQ lines
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- Most onchip peripherals are wired directly to an L1 input
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- A separate instance of the register set for each CPU, allowing individual
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peripheral IRQs to be routed to any CPU
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- Contains one or more enable/status word pairs per CPU
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- No atomic set/clear operations
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- No polarity/level/edge settings
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- No FIFO or priority encoder logic; software is expected to read all
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2-4 status words to determine which IRQs are pending
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If multiple reg ranges and interrupt-parent entries are present on an SMP
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system, the driver will allow IRQ SMP affinity to be set up through the
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/proc/irq/ interface. In the simplest possible configuration, only one
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reg range and one interrupt-parent is needed.
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The driver operates in native CPU endian by default, there is no support for
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specifying an alternative endianness.
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properties:
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compatible:
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const: brcm,bcm6345-l1-intc
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reg:
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description: One entry per CPU core
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minItems: 1
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maxItems: 2
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interrupt-controller: true
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"#interrupt-cells":
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const: 1
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interrupts:
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description: One entry per CPU core
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minItems: 1
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maxItems: 2
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#interrupt-cells'
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- interrupts
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additionalProperties: false
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examples:
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- |
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interrupt-controller@10000000 {
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compatible = "brcm,bcm6345-l1-intc";
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reg = <0x10000020 0x20>,
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<0x10000040 0x20>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts = <2>, <3>;
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};
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