426 lines
13 KiB
YAML
426 lines
13 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SC7280 CAMSS ISP
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maintainers:
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- Azam Sadiq Pasha Kapatrala Syed <akapatra@quicinc.com>
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- Hariram Purushothaman <hariramp@quicinc.com>
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description:
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The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
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properties:
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compatible:
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const: qcom,sc7280-camss
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reg:
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maxItems: 15
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reg-names:
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items:
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- const: csid0
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- const: csid1
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- const: csid2
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- const: csid_lite0
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- const: csid_lite1
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- const: csiphy0
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- const: csiphy1
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- const: csiphy2
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- const: csiphy3
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- const: csiphy4
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- const: vfe0
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- const: vfe1
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- const: vfe2
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- const: vfe_lite0
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- const: vfe_lite1
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clocks:
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maxItems: 33
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clock-names:
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items:
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- const: camnoc_axi
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- const: cpas_ahb
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- const: csiphy0
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- const: csiphy0_timer
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- const: csiphy1
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- const: csiphy1_timer
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- const: csiphy2
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- const: csiphy2_timer
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- const: csiphy3
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- const: csiphy3_timer
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- const: csiphy4
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- const: csiphy4_timer
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- const: gcc_axi_hf
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- const: gcc_axi_sf
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- const: icp_ahb
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- const: vfe0
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- const: vfe0_axi
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- const: vfe0_cphy_rx
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- const: vfe0_csid
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- const: vfe1
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- const: vfe1_axi
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- const: vfe1_cphy_rx
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- const: vfe1_csid
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- const: vfe2
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- const: vfe2_axi
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- const: vfe2_cphy_rx
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- const: vfe2_csid
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- const: vfe_lite0
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- const: vfe_lite0_cphy_rx
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- const: vfe_lite0_csid
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- const: vfe_lite1
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- const: vfe_lite1_cphy_rx
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- const: vfe_lite1_csid
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interrupts:
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maxItems: 15
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interrupt-names:
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items:
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- const: csid0
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- const: csid1
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- const: csid2
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- const: csid_lite0
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- const: csid_lite1
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- const: csiphy0
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- const: csiphy1
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- const: csiphy2
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- const: csiphy3
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- const: csiphy4
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- const: vfe0
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- const: vfe1
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- const: vfe2
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- const: vfe_lite0
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- const: vfe_lite1
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interconnects:
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maxItems: 2
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interconnect-names:
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items:
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- const: ahb
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- const: hf_0
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iommus:
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maxItems: 1
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power-domains:
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items:
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- description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
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- description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
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- description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
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- description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
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power-domain-names:
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items:
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- const: ife0
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- const: ife1
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- const: ife2
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- const: top
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vdda-phy-supply:
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description:
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Phandle to a regulator supply to PHY core block.
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vdda-pll-supply:
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description:
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Phandle to 1.8V regulator supply to PHY refclk pll block.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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CSI input ports.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data on CSIPHY 0.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- data-lanes
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port@1:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data on CSIPHY 1.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- data-lanes
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port@2:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data on CSIPHY 2.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- data-lanes
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port@3:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data on CSIPHY 3.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- data-lanes
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port@4:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data on CSIPHY 4.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- data-lanes
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- interconnects
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- interconnect-names
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- iommus
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- power-domains
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- power-domain-names
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- vdda-phy-supply
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- vdda-pll-supply
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,camcc-sc7280.h>
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#include <dt-bindings/clock/qcom,gcc-sc7280.h>
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#include <dt-bindings/interconnect/qcom,sc7280.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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isp@acb3000 {
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compatible = "qcom,sc7280-camss";
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reg = <0x0 0x0acb3000 0x0 0x1000>,
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<0x0 0x0acba000 0x0 0x1000>,
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<0x0 0x0acc1000 0x0 0x1000>,
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<0x0 0x0acc8000 0x0 0x1000>,
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<0x0 0x0accf000 0x0 0x1000>,
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<0x0 0x0ace0000 0x0 0x2000>,
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<0x0 0x0ace2000 0x0 0x2000>,
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<0x0 0x0ace4000 0x0 0x2000>,
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<0x0 0x0ace6000 0x0 0x2000>,
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<0x0 0x0ace8000 0x0 0x2000>,
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<0x0 0x0acaf000 0x0 0x4000>,
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<0x0 0x0acb6000 0x0 0x4000>,
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<0x0 0x0acbd000 0x0 0x4000>,
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<0x0 0x0acc4000 0x0 0x4000>,
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<0x0 0x0accb000 0x0 0x4000>;
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reg-names = "csid0",
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"csid1",
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"csid2",
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"csid_lite0",
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"csid_lite1",
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"csiphy0",
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"csiphy1",
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"csiphy2",
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"csiphy3",
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"csiphy4",
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"vfe0",
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"vfe1",
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"vfe2",
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"vfe_lite0",
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"vfe_lite1";
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clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
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<&camcc CAM_CC_CSIPHY0_CLK>,
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<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY1_CLK>,
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<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY2_CLK>,
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<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY3_CLK>,
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<&camcc CAM_CC_CSI3PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY4_CLK>,
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<&camcc CAM_CC_CSI4PHYTIMER_CLK>,
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<&gcc GCC_CAMERA_HF_AXI_CLK>,
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<&gcc GCC_CAMERA_SF_AXI_CLK>,
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<&camcc CAM_CC_ICP_AHB_CLK>,
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<&camcc CAM_CC_IFE_0_CLK>,
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<&camcc CAM_CC_IFE_0_AXI_CLK>,
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<&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_0_CSID_CLK>,
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<&camcc CAM_CC_IFE_1_CLK>,
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<&camcc CAM_CC_IFE_1_AXI_CLK>,
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<&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_1_CSID_CLK>,
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<&camcc CAM_CC_IFE_2_CLK>,
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<&camcc CAM_CC_IFE_2_AXI_CLK>,
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<&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_2_CSID_CLK>,
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<&camcc CAM_CC_IFE_LITE_0_CLK>,
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<&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
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<&camcc CAM_CC_IFE_LITE_1_CLK>,
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<&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_LITE_1_CSID_CLK>;
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clock-names = "camnoc_axi",
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"cpas_ahb",
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"csiphy0",
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"csiphy0_timer",
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"csiphy1",
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"csiphy1_timer",
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"csiphy2",
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"csiphy2_timer",
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"csiphy3",
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"csiphy3_timer",
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"csiphy4",
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"csiphy4_timer",
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"gcc_axi_hf",
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"gcc_axi_sf",
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"icp_ahb",
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"vfe0",
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"vfe0_axi",
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"vfe0_cphy_rx",
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"vfe0_csid",
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"vfe1",
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"vfe1_axi",
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"vfe1_cphy_rx",
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"vfe1_csid",
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"vfe2",
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"vfe2_axi",
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"vfe2_cphy_rx",
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"vfe2_csid",
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"vfe_lite0",
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"vfe_lite0_cphy_rx",
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"vfe_lite0_csid",
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"vfe_lite1",
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"vfe_lite1_cphy_rx",
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"vfe_lite1_csid";
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interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csid0",
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"csid1",
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"csid2",
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"csid_lite0",
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"csid_lite1",
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"csiphy0",
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"csiphy1",
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"csiphy2",
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"csiphy3",
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"csiphy4",
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"vfe0",
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"vfe1",
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"vfe2",
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"vfe_lite0",
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"vfe_lite1";
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "ahb",
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"hf_0";
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iommus = <&apps_smmu 0x800 0x4e0>;
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power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
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<&camcc CAM_CC_IFE_1_GDSC>,
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<&camcc CAM_CC_IFE_2_GDSC>,
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<&camcc CAM_CC_TITAN_TOP_GDSC>;
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power-domain-names = "ife0",
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"ife1",
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"ife2",
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"top";
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vdda-phy-supply = <&vreg_l10c_0p88>;
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vdda-pll-supply = <&vreg_l6b_1p2>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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