58 lines
1.6 KiB
YAML
58 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mips/mti,mips-cm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MIPS Coherence Manager
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description:
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The Coherence Manager (CM) is responsible for establishing the
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global ordering of requests from all elements of the system and
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sending the correct data back to the requester. It supports Cache
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to Cache transfers.
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https://training.mips.com/cps_mips/PDF/CPS_Introduction.pdf
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https://training.mips.com/cps_mips/PDF/Coherency_Manager.pdf
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maintainers:
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- Jiaxun Yang <jiaxun.yang@flygoat.com>
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properties:
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compatible:
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oneOf:
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- const: mti,mips-cm
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- const: mobileye,eyeq6-cm
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description:
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On EyeQ6 the HCI (Hardware Cache Initialization) information for
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the L2 cache in multi-cluster configuration is broken.
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reg:
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description:
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Base address and size of the Global Configuration Registers
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referred to as CMGCR.They are the system programmer's interface
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to the Coherency Manager. Their location in the memory map is
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determined at core build time. In a functional system, the base
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address is provided by the Coprocessor 0, but some
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System-on-Chip (SoC) designs may not provide an accurate address
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that needs to be described statically.
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maxItems: 1
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required:
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- compatible
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additionalProperties: false
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examples:
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- |
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coherency-manager@1fbf8000 {
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compatible = "mti,mips-cm";
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reg = <0x1bde8000 0x8000>;
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};
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- |
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coherency-manager {
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compatible = "mobileye,eyeq6-cm";
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};
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...
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