534 lines
21 KiB
YAML
534 lines
21 KiB
YAML
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/qcom,ipq9574-ppe.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm IPQ packet process engine (PPE)
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maintainers:
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- Luo Jie <quic_luoj@quicinc.com>
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- Lei Wei <quic_leiwei@quicinc.com>
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- Suruchi Agarwal <quic_suruchia@quicinc.com>
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- Pavithra R <quic_pavir@quicinc.com>
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description: |
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The Ethernet functionality in the PPE (Packet Process Engine) is comprised
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of three components, the switch core, port wrapper and Ethernet DMA.
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The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and
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two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet
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port to host CPU communication using Ethernet DMA. The other is used
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communicating to the EIP engine which is used for IPsec offload. On the
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IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external
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Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue
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Management) and SCH (Scheduler) modules for supporting the packet processing.
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The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS)
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supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There
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are 3 UNIPHY (PCS) instances supported on the IPQ9574.
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Ethernet DMA is used to transmit and receive packets between the six Ethernet
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ports and ARM host CPU.
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The follow diagram shows the PPE hardware block along with its connectivity
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to the external hardware blocks such clock hardware blocks (CMNPLL, GCC,
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NSS clock controller) and Ethernet PCS/PHY blocks. For depicting the PHY
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connectivity, one 4x1 Gbps PHY (QCA8075) and two 10 GBps PHYs are used as an
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example.
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+---------+
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| 48 MHZ |
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+----+----+
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|(clock)
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v
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+----+----+
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+------| CMN PLL |
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| +----+----+
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| |(clock)
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| v
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| +----+----+ +----+----+ (clock) +----+----+
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| +---| NSSCC | | GCC |--------->| MDIO |
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| | +----+----+ +----+----+ +----+----+
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| | |(clock & reset) |(clock)
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| | v v
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| | +----+---------------------+--+----------+----------+---------+
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| | | +-----+ |EDMA FIFO | | EIP FIFO|
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| | | | SCH | +----------+ +---------+
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| | | +-----+ | | |
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| | | +------+ +------+ +-------------------+ |
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| | | | BM | | QM | IPQ9574-PPE | L2/L3 Process | |
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| | | +------+ +------+ +-------------------+ |
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| | | | |
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| | | +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ |
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| | | | MAC0 | | MAC1 | | MAC2 | | MAC3 | | XGMAC4| |XGMAC5 | |
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| | | +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ |
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| | | | | | | | | |
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| | +-----+---------+---------+---------+---------+---------+-----+
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| | | | | | | |
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| | +---+---------+---------+---------+---+ +---+---+ +---+---+
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+--+---->| PCS0 | | PCS1 | | PCS2 |
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|(clock) +---+---------+---------+---------+---+ +---+---+ +---+---+
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| | | | | | |
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| +---+---------+---------+---------+---+ +---+---+ +---+---+
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+------->| QCA8075 PHY | | PHY4 | | PHY5 |
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(clock) +-------------------------------------+ +-------+ +-------+
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properties:
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compatible:
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enum:
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- qcom,ipq9574-ppe
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reg:
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maxItems: 1
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clocks:
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items:
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- description: PPE core clock
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- description: PPE APB (Advanced Peripheral Bus) clock
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- description: PPE IPE (Ingress Process Engine) clock
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- description: PPE BM, QM and scheduler clock
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clock-names:
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items:
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- const: ppe
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- const: apb
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- const: ipe
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- const: btq
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resets:
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maxItems: 1
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description: PPE reset, which is necessary before configuring PPE hardware
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interrupts:
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maxItems: 1
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description: PPE switch miscellaneous interrupt
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interconnects:
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items:
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- description: Bus interconnect path leading to PPE switch core function
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- description: Bus interconnect path leading to PPE register access
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- description: Bus interconnect path leading to QoS generation
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- description: Bus interconnect path leading to timeout reference
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- description: Bus interconnect path leading to NSS NOC from memory NOC
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- description: Bus interconnect path leading to memory NOC from NSS NOC
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- description: Bus interconnect path leading to enhanced memory NOC from NSS NOC
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interconnect-names:
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items:
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- const: ppe
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- const: ppe_cfg
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- const: qos_gen
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- const: timeout_ref
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- const: nssnoc_memnoc
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- const: memnoc_nssnoc
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- const: memnoc_nssnoc_1
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ethernet-dma:
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type: object
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additionalProperties: false
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description:
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EDMA (Ethernet DMA) is used to transmit packets between PPE and ARM
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host CPU. There are 32 TX descriptor rings, 32 TX completion rings,
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24 RX descriptor rings and 8 RX fill rings supported.
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properties:
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clocks:
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items:
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- description: EDMA system clock
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- description: EDMA APB (Advanced Peripheral Bus) clock
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clock-names:
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items:
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- const: sys
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- const: apb
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resets:
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maxItems: 1
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description: EDMA reset
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interrupts:
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minItems: 65
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maxItems: 65
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interrupt-names:
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minItems: 65
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maxItems: 65
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items:
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oneOf:
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- pattern: '^txcmpl_([1-2]?[0-9]|3[01])$'
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- pattern: '^rxfill_[0-7]$'
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- pattern: '^rxdesc_(1?[0-9]|2[0-3])$'
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- const: misc
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description:
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Interrupts "txcmpl_[0-31]" are the Ethernet DMA TX completion ring interrupts.
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Interrupts "rxfill_[0-7]" are the Ethernet DMA RX fill ring interrupts.
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Interrupts "rxdesc_[0-23]" are the Ethernet DMA RX Descriptor ring interrupts.
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Interrupt "misc" is the Ethernet DMA miscellaneous error interrupt.
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required:
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- clocks
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- clock-names
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- resets
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- interrupts
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- interrupt-names
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ethernet-ports:
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patternProperties:
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"^ethernet-port@[1-6]+$":
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type: object
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unevaluatedProperties: false
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$ref: ethernet-switch-port.yaml#
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properties:
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reg:
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minimum: 1
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maximum: 6
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description: PPE Ethernet port ID
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clocks:
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items:
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- description: Port MAC clock
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- description: Port RX clock
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- description: Port TX clock
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clock-names:
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items:
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- const: mac
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- const: rx
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- const: tx
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resets:
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items:
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- description: Port MAC reset
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- description: Port RX reset
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- description: Port TX reset
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reset-names:
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items:
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- const: mac
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- const: rx
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- const: tx
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required:
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- interconnects
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- interconnect-names
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- ethernet-dma
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allOf:
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- $ref: ethernet-switch.yaml
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
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#include <dt-bindings/interconnect/qcom,ipq9574.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
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ethernet-switch@3a000000 {
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compatible = "qcom,ipq9574-ppe";
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reg = <0x3a000000 0xbef800>;
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clocks = <&nsscc NSS_CC_PPE_SWITCH_CLK>,
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<&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>,
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<&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>,
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<&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>;
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clock-names = "ppe",
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"apb",
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"ipe",
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"btq";
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resets = <&nsscc PPE_FULL_RESET>;
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interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&nsscc MASTER_NSSNOC_PPE &nsscc SLAVE_NSSNOC_PPE>,
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<&nsscc MASTER_NSSNOC_PPE_CFG &nsscc SLAVE_NSSNOC_PPE_CFG>,
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<&gcc MASTER_NSSNOC_QOSGEN_REF &gcc SLAVE_NSSNOC_QOSGEN_REF>,
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<&gcc MASTER_NSSNOC_TIMEOUT_REF &gcc SLAVE_NSSNOC_TIMEOUT_REF>,
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<&gcc MASTER_MEM_NOC_NSSNOC &gcc SLAVE_MEM_NOC_NSSNOC>,
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<&gcc MASTER_NSSNOC_MEMNOC &gcc SLAVE_NSSNOC_MEMNOC>,
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<&gcc MASTER_NSSNOC_MEM_NOC_1 &gcc SLAVE_NSSNOC_MEM_NOC_1>;
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interconnect-names = "ppe",
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"ppe_cfg",
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"qos_gen",
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"timeout_ref",
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"nssnoc_memnoc",
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"memnoc_nssnoc",
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"memnoc_nssnoc_1";
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ethernet-dma {
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clocks = <&nsscc NSS_CC_PPE_EDMA_CLK>,
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<&nsscc NSS_CC_PPE_EDMA_CFG_CLK>;
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clock-names = "sys",
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"apb";
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resets = <&nsscc EDMA_HW_RESET>;
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interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "txcmpl_0",
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"txcmpl_1",
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"txcmpl_2",
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"txcmpl_3",
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"txcmpl_4",
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"txcmpl_5",
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"txcmpl_6",
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"txcmpl_7",
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"txcmpl_8",
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"txcmpl_9",
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"txcmpl_10",
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"txcmpl_11",
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"txcmpl_12",
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"txcmpl_13",
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"txcmpl_14",
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"txcmpl_15",
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"txcmpl_16",
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"txcmpl_17",
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"txcmpl_18",
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"txcmpl_19",
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"txcmpl_20",
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"txcmpl_21",
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"txcmpl_22",
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"txcmpl_23",
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"txcmpl_24",
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"txcmpl_25",
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"txcmpl_26",
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"txcmpl_27",
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"txcmpl_28",
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"txcmpl_29",
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"txcmpl_30",
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"txcmpl_31",
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"rxfill_0",
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"rxfill_1",
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"rxfill_2",
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"rxfill_3",
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"rxfill_4",
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"rxfill_5",
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"rxfill_6",
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"rxfill_7",
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"rxdesc_0",
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"rxdesc_1",
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"rxdesc_2",
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"rxdesc_3",
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"rxdesc_4",
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"rxdesc_5",
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"rxdesc_6",
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"rxdesc_7",
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"rxdesc_8",
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"rxdesc_9",
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"rxdesc_10",
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"rxdesc_11",
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"rxdesc_12",
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"rxdesc_13",
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"rxdesc_14",
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"rxdesc_15",
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"rxdesc_16",
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"rxdesc_17",
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"rxdesc_18",
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"rxdesc_19",
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"rxdesc_20",
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"rxdesc_21",
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"rxdesc_22",
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"rxdesc_23",
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"misc";
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};
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-port@1 {
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reg = <1>;
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phy-mode = "qsgmii";
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managed = "in-band-status";
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phy-handle = <&phy0>;
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pcs-handle = <&pcs0_ch0>;
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clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>,
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<&nsscc NSS_CC_PORT1_RX_CLK>,
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<&nsscc NSS_CC_PORT1_TX_CLK>;
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clock-names = "mac",
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"rx",
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"tx";
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resets = <&nsscc PORT1_MAC_ARES>,
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<&nsscc PORT1_RX_ARES>,
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<&nsscc PORT1_TX_ARES>;
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reset-names = "mac",
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"rx",
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"tx";
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};
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ethernet-port@2 {
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reg = <2>;
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phy-mode = "qsgmii";
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managed = "in-band-status";
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phy-handle = <&phy1>;
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pcs-handle = <&pcs0_ch1>;
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clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>,
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<&nsscc NSS_CC_PORT2_RX_CLK>,
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<&nsscc NSS_CC_PORT2_TX_CLK>;
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clock-names = "mac",
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"rx",
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"tx";
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resets = <&nsscc PORT2_MAC_ARES>,
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<&nsscc PORT2_RX_ARES>,
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<&nsscc PORT2_TX_ARES>;
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reset-names = "mac",
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"rx",
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"tx";
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};
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ethernet-port@3 {
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reg = <3>;
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phy-mode = "qsgmii";
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managed = "in-band-status";
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phy-handle = <&phy2>;
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pcs-handle = <&pcs0_ch2>;
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clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>,
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<&nsscc NSS_CC_PORT3_RX_CLK>,
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<&nsscc NSS_CC_PORT3_TX_CLK>;
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clock-names = "mac",
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"rx",
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"tx";
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resets = <&nsscc PORT3_MAC_ARES>,
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<&nsscc PORT3_RX_ARES>,
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<&nsscc PORT3_TX_ARES>;
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reset-names = "mac",
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"rx",
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"tx";
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};
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ethernet-port@4 {
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reg = <4>;
|
|
phy-mode = "qsgmii";
|
|
managed = "in-band-status";
|
|
phy-handle = <&phy3>;
|
|
pcs-handle = <&pcs0_ch3>;
|
|
clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>,
|
|
<&nsscc NSS_CC_PORT4_RX_CLK>,
|
|
<&nsscc NSS_CC_PORT4_TX_CLK>;
|
|
clock-names = "mac",
|
|
"rx",
|
|
"tx";
|
|
resets = <&nsscc PORT4_MAC_ARES>,
|
|
<&nsscc PORT4_RX_ARES>,
|
|
<&nsscc PORT4_TX_ARES>;
|
|
reset-names = "mac",
|
|
"rx",
|
|
"tx";
|
|
};
|
|
|
|
ethernet-port@5 {
|
|
reg = <5>;
|
|
phy-mode = "usxgmii";
|
|
managed = "in-band-status";
|
|
phy-handle = <&phy4>;
|
|
pcs-handle = <&pcs1_ch0>;
|
|
clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>,
|
|
<&nsscc NSS_CC_PORT5_RX_CLK>,
|
|
<&nsscc NSS_CC_PORT5_TX_CLK>;
|
|
clock-names = "mac",
|
|
"rx",
|
|
"tx";
|
|
resets = <&nsscc PORT5_MAC_ARES>,
|
|
<&nsscc PORT5_RX_ARES>,
|
|
<&nsscc PORT5_TX_ARES>;
|
|
reset-names = "mac",
|
|
"rx",
|
|
"tx";
|
|
};
|
|
|
|
ethernet-port@6 {
|
|
reg = <6>;
|
|
phy-mode = "usxgmii";
|
|
managed = "in-band-status";
|
|
phy-handle = <&phy5>;
|
|
pcs-handle = <&pcs2_ch0>;
|
|
clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>,
|
|
<&nsscc NSS_CC_PORT6_RX_CLK>,
|
|
<&nsscc NSS_CC_PORT6_TX_CLK>;
|
|
clock-names = "mac",
|
|
"rx",
|
|
"tx";
|
|
resets = <&nsscc PORT6_MAC_ARES>,
|
|
<&nsscc PORT6_RX_ARES>,
|
|
<&nsscc PORT6_TX_ARES>;
|
|
reset-names = "mac",
|
|
"rx",
|
|
"tx";
|
|
};
|
|
};
|
|
};
|