134 lines
4.4 KiB
YAML
134 lines
4.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,glymur-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Glymur TLMM block
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maintainers:
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- Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,glymur-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 125
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gpio-line-names:
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maxItems: 250
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-glymur-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-glymur-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-glymur-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-4][0-9])$"
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- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ gpio, resout_gpio_n, aoss_cti, asc_cci, atest_char, atest_usb,
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audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk, cam_asc_mclk4,
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cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer,
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cmu_rng, cri_trng, dbg_out_clk, ddr_bist_complete,
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ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi,
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edp0_hot, edp0_lcd, edp1_lcd, egpio, eusb0_ac_en, eusb1_ac_en,
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eusb2_ac_en, eusb3_ac_en, eusb5_ac_en, eusb6_ac_en, gcc_gp1,
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gcc_gp2, gcc_gp3, host2wlan_sol, i2c0_s_scl, i2c0_s_sda,
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i2s0_data, i2s0_sck, i2s0_ws, i2s1_data, i2s1_sck, i2s1_ws,
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ibi_i3c, jitter_bist, mdp_vsync_out, mdp_vsync_e, mdp_vsync_p,
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mdp_vsync_s, pcie3a_clk, pcie3a_rst_n, pcie3b_clk,
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pcie4_clk_req_n, pcie5_clk_req_n, pcie6_clk_req_n, phase_flag,
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pll_bist_sync, pll_clk_aux, pmc_oca_n, pmc_uva_n, prng_rosc,
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qdss_cti, qdss_gpio, qspi, qup0_se0, qup0_se1, qup0_se2,
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qup0_se3_l0, qup0_se3, qup0_se4, qup0_se5, qup0_se6, qup0_se7,
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qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5,
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qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3,
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qup2_se4, qup2_se5, qup2_se6, qup2_se7, qup3_se0, qup3_se1,
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sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data, smb_acok_n,
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sys_throttle, tb_trig_sdc2, tb_trig_sdc4, tmess_prng,
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tsense_pwm, tsense_therm, usb0_dp, usb0_phy_ps, usb0_sbrx,
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usb0_sbtx, usb0_tmu, usb1_dbg, usb1_dp, usb1_phy_ps, usb1_sbrx,
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usb1_sbtx, usb1_tmu, usb2_dp, usb2_phy_ps, usb2_sbrx, usb2_sbtx,
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usb2_tmu, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ]
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required:
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- pins
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@f100000 {
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compatible = "qcom,glymur-tlmm";
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reg = <0x0f100000 0xf00000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 249>;
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wakeup-parent = <&pdc>;
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gpio-reserved-ranges = <4 4>, <10 2>, <33 3>, <44 4>;
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qup_uart21_default: qup-uart21-default-state {
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tx-pins {
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pins = "gpio86";
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function = "qup2_se5";
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drive-strength = <2>;
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bias-disable;
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};
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rx-pins {
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pins = "gpio87";
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function = "qup2_se5";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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...
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