Linux-6.18.2/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 BayLibre, SAS
 * Author: Neil Armstrong <narmstrong@baylibre.com>
 */

#include "meson-g12.dtsi"

/ {
	compatible = "amlogic,g12b";

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu100>;
				};

				core1 {
					cpu = <&cpu101>;
				};

				core2 {
					cpu = <&cpu102>;
				};

				core3 {
					cpu = <&cpu103>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			enable-method = "psci";
			capacity-dmips-mhz = <592>;
			d-cache-line-size = <32>;
			d-cache-size = <0x8000>;
			d-cache-sets = <32>;
			i-cache-line-size = <32>;
			i-cache-size = <0x8000>;
			i-cache-sets = <32>;
			next-level-cache = <&l2_cache_l>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			enable-method = "psci";
			capacity-dmips-mhz = <592>;
			d-cache-line-size = <32>;
			d-cache-size = <0x8000>;
			d-cache-sets = <32>;
			i-cache-line-size = <32>;
			i-cache-size = <0x8000>;
			i-cache-sets = <32>;
			next-level-cache = <&l2_cache_l>;
			#cooling-cells = <2>;
		};

		cpu100: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			d-cache-line-size = <32>;
			d-cache-size = <0x8000>;
			d-cache-sets = <32>;
			i-cache-line-size = <32>;
			i-cache-size = <0x8000>;
			i-cache-sets = <32>;
			next-level-cache = <&l2_cache_b>;
			#cooling-cells = <2>;
		};

		cpu101: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x101>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			d-cache-line-size = <32>;
			d-cache-size = <0x8000>;
			d-cache-sets = <32>;
			i-cache-line-size = <32>;
			i-cache-size = <0x8000>;
			i-cache-sets = <32>;
			next-level-cache = <&l2_cache_b>;
			#cooling-cells = <2>;
		};

		cpu102: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x102>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			d-cache-line-size = <64>;
			d-cache-size = <0x10000>;
			d-cache-sets = <64>;
			i-cache-line-size = <64>;
			i-cache-size = <0x10000>;
			i-cache-sets = <64>;
			next-level-cache = <&l2_cache_b>;
			#cooling-cells = <2>;
		};

		cpu103: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x103>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			d-cache-line-size = <64>;
			d-cache-size = <0x10000>;
			d-cache-sets = <64>;
			i-cache-line-size = <64>;
			i-cache-size = <0x10000>;
			i-cache-sets = <64>;
			next-level-cache = <&l2_cache_b>;
			#cooling-cells = <2>;
		};

		l2_cache_l: l2-cache-cluster0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x40000>;  /* L2. 256 KB */
			cache-line-size = <64>;
			cache-sets = <512>;
		};

		l2_cache_b: l2-cache-cluster1 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x100000>; /* L2. 1MB */
			cache-line-size = <64>;
			cache-sets = <512>;
		};
	};
};

&clkc {
	compatible = "amlogic,g12b-clkc";
};

&cpu_thermal {
	cooling-maps {
		map0 {
			trip = <&cpu_passive>;
			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					 <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					 <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
		};
		map1 {
			trip = <&cpu_hot>;
			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					 <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					 <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
		};
	};
};

&mali {
	dma-coherent;
};

&pmu {
	compatible = "amlogic,g12b-ddr-pmu";
};

&npu {
	power-domains = <&pwrc PWRC_G12A_NNA_ID>;
};