250 lines
6.5 KiB
Plaintext
250 lines
6.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Apple S8000/S8003 "A9" SoC
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*
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* This file contains parts common to both variants of A9
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*
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* Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/apple-aic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/apple.h>
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/ {
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interrupt-parent = <&aic>;
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#address-cells = <2>;
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#size-cells = <2>;
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clkref: clock-ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "clkref";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "apple,twister";
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reg = <0x0 0x0>;
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cpu-release-addr = <0 0>; /* To be filled in by loader */
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operating-points-v2 = <&twister_opp>;
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performance-domains = <&cpufreq>;
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enable-method = "spin-table";
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device_type = "cpu";
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next-level-cache = <&l2_cache>;
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i-cache-size = <0x10000>;
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d-cache-size = <0x10000>;
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};
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cpu1: cpu@1 {
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compatible = "apple,twister";
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reg = <0x0 0x1>;
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cpu-release-addr = <0 0>; /* To be filled in by loader */
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operating-points-v2 = <&twister_opp>;
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performance-domains = <&cpufreq>;
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enable-method = "spin-table";
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device_type = "cpu";
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next-level-cache = <&l2_cache>;
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i-cache-size = <0x10000>;
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d-cache-size = <0x10000>;
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};
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l2_cache: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x300000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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nonposted-mmio;
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ranges;
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cpufreq: performance-controller@202220000 {
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compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
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reg = <0x2 0x02220000 0 0x1000>;
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#performance-domain-cells = <0>;
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};
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serial0: serial@20a0c0000 {
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compatible = "apple,s5l-uart";
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reg = <0x2 0x0a0c0000 0x0 0x4000>;
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reg-io-width = <4>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>;
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/* Use the bootloader-enabled clocks for now. */
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clocks = <&clkref>, <&clkref>;
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clock-names = "uart", "clk_uart_baud0";
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power-domains = <&ps_uart0>;
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status = "disabled";
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};
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i2c0: i2c@20a110000 {
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compatible = "apple,s8000-i2c", "apple,i2c";
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reg = <0x2 0x0a110000 0x0 0x1000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 206 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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power-domains = <&ps_i2c0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@20a111000 {
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compatible = "apple,s8000-i2c", "apple,i2c";
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reg = <0x2 0x0a111000 0x0 0x1000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 207 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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power-domains = <&ps_i2c1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@20a112000 {
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compatible = "apple,s8000-i2c", "apple,i2c";
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reg = <0x2 0x0a112000 0x0 0x1000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 208 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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power-domains = <&ps_i2c2>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pmgr: power-management@20e000000 {
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compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x2 0xe000000 0 0x8c000>;
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};
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aic: interrupt-controller@20e100000 {
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compatible = "apple,s8000-aic", "apple,aic";
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reg = <0x2 0x0e100000 0x0 0x100000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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power-domains = <&ps_aic>;
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};
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dwi_bl: backlight@20e200080 {
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compatible = "apple,s8000-dwi-bl", "apple,dwi-bl";
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reg = <0x2 0x0e200080 0x0 0x8>;
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power-domains = <&ps_dwi>;
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status = "disabled";
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};
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pinctrl_ap: pinctrl@20f100000 {
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compatible = "apple,s8000-pinctrl", "apple,pinctrl";
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reg = <0x2 0x0f100000 0x0 0x100000>;
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power-domains = <&ps_gpio>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_ap 0 0 208>;
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apple,npins = <208>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>;
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i2c0_pins: i2c0-pins {
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pinmux = <APPLE_PINMUX(46, 1)>,
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<APPLE_PINMUX(45, 1)>;
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};
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i2c1_pins: i2c1-pins {
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pinmux = <APPLE_PINMUX(115, 1)>,
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<APPLE_PINMUX(114, 1)>;
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};
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i2c2_pins: i2c2-pins {
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pinmux = <APPLE_PINMUX(23, 1)>,
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<APPLE_PINMUX(22, 1)>;
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};
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};
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pinctrl_aop: pinctrl@2100f0000 {
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compatible = "apple,s8000-pinctrl", "apple,pinctrl";
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reg = <0x2 0x100f0000 0x0 0x100000>;
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power-domains = <&ps_aop_gpio>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aop 0 0 42>;
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apple,npins = <42>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 115 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 116 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 117 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 118 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 119 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmgr_mini: power-management@210200000 {
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compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x2 0x10200000 0 0x84000>;
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};
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wdt: watchdog@2102b0000 {
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compatible = "apple,s8000-wdt", "apple,wdt";
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reg = <0x2 0x102b0000 0x0 0x4000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&aic>;
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interrupt-names = "phys", "virt";
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/* Note that A9 doesn't actually have a hypervisor (EL2 is not implemented). */
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interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
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<AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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#include "s800-0-3-pmgr.dtsi"
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/*
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* The A9 was made by two separate fabs on two different process
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* nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made
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* the S8003 (APL1022) on 16nm. There are some minor differences
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* such as timing in cpufreq state transistions.
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*/
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