288 lines
7.1 KiB
Plaintext
288 lines
7.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Apple T7000 "A8" SoC
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*
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* Other names: H7P, "Fiji"
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*
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* Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org>
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* Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/apple-aic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/apple.h>
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/ {
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interrupt-parent = <&aic>;
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#address-cells = <2>;
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#size-cells = <2>;
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clkref: clock-ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "clkref";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "apple,typhoon";
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reg = <0x0 0x0>;
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cpu-release-addr = <0 0>; /* To be filled in by loader */
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performance-domains = <&cpufreq>;
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operating-points-v2 = <&typhoon_opp>;
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enable-method = "spin-table";
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device_type = "cpu";
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next-level-cache = <&l2_cache>;
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i-cache-size = <0x10000>;
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d-cache-size = <0x10000>;
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};
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cpu1: cpu@1 {
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compatible = "apple,typhoon";
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reg = <0x0 0x1>;
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cpu-release-addr = <0 0>; /* To be filled in by loader */
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performance-domains = <&cpufreq>;
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operating-points-v2 = <&typhoon_opp>;
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enable-method = "spin-table";
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device_type = "cpu";
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next-level-cache = <&l2_cache>;
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i-cache-size = <0x10000>;
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d-cache-size = <0x10000>;
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};
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l2_cache: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x100000>;
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};
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};
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typhoon_opp: opp-table {
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compatible = "operating-points-v2";
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opp01 {
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opp-hz = /bits/ 64 <300000000>;
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opp-level = <1>;
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clock-latency-ns = <300>;
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};
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opp02 {
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opp-hz = /bits/ 64 <396000000>;
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opp-level = <2>;
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clock-latency-ns = <50000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <600000000>;
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opp-level = <3>;
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clock-latency-ns = <29000>;
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};
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opp04 {
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opp-hz = /bits/ 64 <840000000>;
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opp-level = <4>;
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clock-latency-ns = <29000>;
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};
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opp05 {
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opp-hz = /bits/ 64 <1128000000>;
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opp-level = <5>;
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clock-latency-ns = <36000>;
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};
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typhoon_opp06: opp06 {
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opp-hz = /bits/ 64 <1392000000>;
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opp-level = <6>;
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clock-latency-ns = <42000>;
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status = "disabled"; /* Not available on N102 */
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};
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typhoon_opp07: opp07 {
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opp-hz = /bits/ 64 <1512000000>;
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opp-level = <7>;
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clock-latency-ns = <49000>;
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status = "disabled"; /* J96 and J97 only */
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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nonposted-mmio;
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ranges;
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cpufreq: performance-controller@202220000 {
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compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq";
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reg = <0x2 0x02220000 0 0x1000>;
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#performance-domain-cells = <0>;
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};
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serial0: serial@20a0c0000 {
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compatible = "apple,s5l-uart";
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reg = <0x2 0x0a0c0000 0x0 0x4000>;
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reg-io-width = <4>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 158 IRQ_TYPE_LEVEL_HIGH>;
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/* Use the bootloader-enabled clocks for now. */
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clocks = <&clkref>, <&clkref>;
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clock-names = "uart", "clk_uart_baud0";
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power-domains = <&ps_uart0>;
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status = "disabled";
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};
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serial6: serial@20a0d8000 {
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compatible = "apple,s5l-uart";
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reg = <0x2 0x0a0d8000 0x0 0x4000>;
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reg-io-width = <4>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 164 IRQ_TYPE_LEVEL_HIGH>;
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/* Use the bootloader-enabled clocks for now. */
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clocks = <&clkref>, <&clkref>;
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clock-names = "uart", "clk_uart_baud0";
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power-domains = <&ps_uart6>;
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status = "disabled";
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};
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i2c0: i2c@20a110000 {
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compatible = "apple,t7000-i2c", "apple,i2c";
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reg = <0x2 0x0a110000 0x0 0x1000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 174 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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power-domains = <&ps_i2c0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@20a111000 {
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compatible = "apple,t7000-i2c", "apple,i2c";
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reg = <0x2 0x0a111000 0x0 0x1000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 175 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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power-domains = <&ps_i2c1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@20a112000 {
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compatible = "apple,t7000-i2c", "apple,i2c";
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reg = <0x2 0x0a112000 0x0 0x1000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 176 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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power-domains = <&ps_i2c2>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@20a113000 {
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compatible = "apple,t7000-i2c", "apple,i2c";
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reg = <0x2 0x0a113000 0x0 0x1000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 177 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&i2c3_pins>;
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pinctrl-names = "default";
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power-domains = <&ps_i2c3>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pmgr: power-management@20e000000 {
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compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x2 0xe000000 0 0x24000>;
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};
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wdt: watchdog@20e027000 {
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compatible = "apple,t7000-wdt", "apple,wdt";
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reg = <0x2 0x0e027000 0x0 0x1000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>;
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};
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aic: interrupt-controller@20e100000 {
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compatible = "apple,t7000-aic", "apple,aic";
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reg = <0x2 0x0e100000 0x0 0x100000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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power-domains = <&ps_aic>;
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};
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dwi_bl: backlight@20e200010 {
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compatible = "apple,t7000-dwi-bl", "apple,dwi-bl";
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reg = <0x2 0x0e200010 0x0 0x8>;
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power-domains = <&ps_dwi>;
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status = "disabled";
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};
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pinctrl: pinctrl@20e300000 {
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compatible = "apple,t7000-pinctrl", "apple,pinctrl";
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reg = <0x2 0x0e300000 0x0 0x100000>;
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power-domains = <&ps_gpio>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 208>;
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apple,npins = <208>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 62 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 63 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 64 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 65 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 66 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 67 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 68 IRQ_TYPE_LEVEL_HIGH>;
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i2c0_pins: i2c0-pins {
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pinmux = <APPLE_PINMUX(97, 1)>,
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<APPLE_PINMUX(96, 1)>;
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};
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i2c1_pins: i2c1-pins {
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pinmux = <APPLE_PINMUX(139, 1)>,
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<APPLE_PINMUX(138, 1)>;
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};
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i2c2_pins: i2c2-pins {
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pinmux = <APPLE_PINMUX(65, 1)>,
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<APPLE_PINMUX(64, 1)>;
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};
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i2c3_pins: i2c3-pins {
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pinmux = <APPLE_PINMUX(87, 1)>,
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<APPLE_PINMUX(86, 1)>;
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&aic>;
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interrupt-names = "phys", "virt";
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/* Note that A8 doesn't actually have a hypervisor (EL2 is not implemented). */
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interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
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<AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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#include "t7000-pmgr.dtsi"
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