536 lines
13 KiB
Plaintext
536 lines
13 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Apple T8015 "A11" SoC
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*
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* Other names: H10, "Skye"
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*
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* Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/apple-aic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/apple.h>
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#include <dt-bindings/spmi/spmi.h>
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/ {
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interrupt-parent = <&aic>;
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#address-cells = <2>;
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#size-cells = <2>;
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clkref: clock-ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "clkref";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu_e0>;
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};
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core1 {
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cpu = <&cpu_e1>;
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};
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core2 {
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cpu = <&cpu_e2>;
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};
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core3 {
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cpu = <&cpu_e3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu_p0>;
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};
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core1 {
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cpu = <&cpu_p1>;
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};
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};
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};
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cpu_e0: cpu@0 {
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compatible = "apple,mistral";
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reg = <0x0 0x0>;
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cpu-release-addr = <0 0>; /* To be filled by loader */
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performance-domains = <&cpufreq_e>;
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operating-points-v2 = <&mistral_opp>;
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capacity-dmips-mhz = <633>;
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enable-method = "spin-table";
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device_type = "cpu";
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next-level-cache = <&l2_cache_0>;
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i-cache-size = <0x8000>;
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d-cache-size = <0x8000>;
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};
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cpu_e1: cpu@1 {
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compatible = "apple,mistral";
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reg = <0x0 0x1>;
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cpu-release-addr = <0 0>; /* To be filled by loader */
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performance-domains = <&cpufreq_e>;
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operating-points-v2 = <&mistral_opp>;
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capacity-dmips-mhz = <633>;
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enable-method = "spin-table";
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device_type = "cpu";
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next-level-cache = <&l2_cache_0>;
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i-cache-size = <0x8000>;
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d-cache-size = <0x8000>;
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};
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cpu_e2: cpu@2 {
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compatible = "apple,mistral";
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reg = <0x0 0x2>;
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cpu-release-addr = <0 0>; /* To be filled by loader */
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performance-domains = <&cpufreq_e>;
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operating-points-v2 = <&mistral_opp>;
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capacity-dmips-mhz = <633>;
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enable-method = "spin-table";
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device_type = "cpu";
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next-level-cache = <&l2_cache_0>;
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i-cache-size = <0x8000>;
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d-cache-size = <0x8000>;
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};
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cpu_e3: cpu@3 {
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compatible = "apple,mistral";
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reg = <0x0 0x3>;
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cpu-release-addr = <0 0>; /* To be filled by loader */
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performance-domains = <&cpufreq_e>;
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operating-points-v2 = <&mistral_opp>;
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capacity-dmips-mhz = <633>;
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enable-method = "spin-table";
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device_type = "cpu";
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next-level-cache = <&l2_cache_0>;
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i-cache-size = <0x8000>;
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d-cache-size = <0x8000>;
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};
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cpu_p0: cpu@10004 {
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compatible = "apple,monsoon";
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reg = <0x0 0x10004>;
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cpu-release-addr = <0 0>; /* To be filled by loader */
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performance-domains = <&cpufreq_p>;
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operating-points-v2 = <&monsoon_opp>;
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capacity-dmips-mhz = <1024>;
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enable-method = "spin-table";
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device_type = "cpu";
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next-level-cache = <&l2_cache_1>;
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i-cache-size = <0x10000>;
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d-cache-size = <0x10000>;
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};
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cpu_p1: cpu@10005 {
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compatible = "apple,monsoon";
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reg = <0x0 0x10005>;
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cpu-release-addr = <0 0>; /* To be filled by loader */
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performance-domains = <&cpufreq_p>;
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operating-points-v2 = <&monsoon_opp>;
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capacity-dmips-mhz = <1024>;
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enable-method = "spin-table";
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device_type = "cpu";
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next-level-cache = <&l2_cache_1>;
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i-cache-size = <0x10000>;
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d-cache-size = <0x10000>;
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};
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l2_cache_0: l2-cache-0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x100000>;
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};
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l2_cache_1: l2-cache-1 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x800000>;
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};
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};
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mistral_opp: opp-table-0 {
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compatible = "operating-points-v2";
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opp01 {
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opp-hz = /bits/ 64 <300000000>;
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opp-level = <1>;
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clock-latency-ns = <1800>;
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};
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opp02 {
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opp-hz = /bits/ 64 <453000000>;
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opp-level = <2>;
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clock-latency-ns = <140000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <672000000>;
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opp-level = <3>;
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clock-latency-ns = <105000>;
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};
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opp04 {
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opp-hz = /bits/ 64 <972000000>;
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opp-level = <4>;
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clock-latency-ns = <115000>;
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};
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opp05 {
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opp-hz = /bits/ 64 <1272000000>;
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opp-level = <5>;
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clock-latency-ns = <125000>;
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};
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opp06 {
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opp-hz = /bits/ 64 <1572000000>;
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opp-level = <6>;
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clock-latency-ns = <135000>;
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};
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#if 0
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/* Not available until CPU deep sleep is implemented */
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opp07 {
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opp-hz = /bits/ 64 <1680000000>;
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opp-level = <7>;
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clock-latency-ns = <135000>;
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turbo-mode;
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};
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#endif
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};
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monsoon_opp: opp-table-1 {
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compatible = "operating-points-v2";
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opp01 {
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opp-hz = /bits/ 64 <300000000>;
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opp-level = <1>;
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clock-latency-ns = <1400>;
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};
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opp02 {
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opp-hz = /bits/ 64 <453000000>;
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opp-level = <2>;
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clock-latency-ns = <140000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <853000000>;
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opp-level = <3>;
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clock-latency-ns = <110000>;
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};
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opp04 {
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opp-hz = /bits/ 64 <1332000000>;
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opp-level = <4>;
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clock-latency-ns = <110000>;
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};
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opp05 {
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opp-hz = /bits/ 64 <1812000000>;
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opp-level = <5>;
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clock-latency-ns = <125000>;
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};
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opp06 {
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opp-hz = /bits/ 64 <2064000000>;
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opp-level = <6>;
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clock-latency-ns = <130000>;
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};
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opp07 {
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opp-hz = /bits/ 64 <2304000000>;
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opp-level = <7>;
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clock-latency-ns = <140000>;
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};
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#if 0
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/* Not available until CPU deep sleep is implemented */
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opp08 {
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opp-hz = /bits/ 64 <2376000000>;
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opp-level = <8>;
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clock-latency-ns = <140000>;
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turbo-mode;
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};
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#endif
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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nonposted-mmio;
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ranges;
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cpufreq_e: performance-controller@208e20000 {
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compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
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reg = <0x2 0x08e20000 0 0x1000>;
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#performance-domain-cells = <0>;
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};
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cpufreq_p: performance-controller@208ea0000 {
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compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
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reg = <0x2 0x08ea0000 0 0x1000>;
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#performance-domain-cells = <0>;
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};
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i2c0: i2c@22e200000 {
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compatible = "apple,t8015-i2c", "apple,i2c";
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reg = <0x2 0x2e200000 0x0 0x1000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 304 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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power-domains = <&ps_i2c0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@22e204000 {
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compatible = "apple,t8015-i2c", "apple,i2c";
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reg = <0x2 0x2e204000 0x0 0x1000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 305 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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power-domains = <&ps_i2c1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@22e208000 {
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compatible = "apple,t8015-i2c", "apple,i2c";
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reg = <0x2 0x2e208000 0x0 0x1000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 306 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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power-domains = <&ps_i2c2>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@22e20c000 {
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compatible = "apple,t8015-i2c", "apple,i2c";
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reg = <0x2 0x2e20c000 0x0 0x1000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 307 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&i2c3_pins>;
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pinctrl-names = "default";
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power-domains = <&ps_i2c3>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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serial0: serial@22e600000 {
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compatible = "apple,s5l-uart";
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reg = <0x2 0x2e600000 0x0 0x4000>;
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reg-io-width = <4>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 282 IRQ_TYPE_LEVEL_HIGH>;
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/* Use the bootloader-enabled clocks for now. */
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clocks = <&clkref>, <&clkref>;
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clock-names = "uart", "clk_uart_baud0";
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power-domains = <&ps_uart0>;
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status = "disabled";
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};
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aic: interrupt-controller@232100000 {
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compatible = "apple,t8015-aic", "apple,aic";
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reg = <0x2 0x32100000 0x0 0x8000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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power-domains = <&ps_aic>;
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};
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pmgr: power-management@232000000 {
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compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x2 0x32000000 0 0x8c000>;
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};
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dwi_bl: backlight@232200080 {
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compatible = "apple,t8015-dwi-bl", "apple,dwi-bl";
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reg = <0x2 0x32200080 0x0 0x8>;
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power-domains = <&ps_dwi>;
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status = "disabled";
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};
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pinctrl_ap: pinctrl@233100000 {
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compatible = "apple,t8015-pinctrl", "apple,pinctrl";
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reg = <0x2 0x33100000 0x0 0x1000>;
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power-domains = <&ps_gpio>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_ap 0 0 223>;
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apple,npins = <223>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 50 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 51 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 52 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 53 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 54 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 55 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 56 IRQ_TYPE_LEVEL_HIGH>;
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i2c0_pins: i2c0-pins {
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pinmux = <APPLE_PINMUX(73, 1)>,
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<APPLE_PINMUX(72, 1)>;
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};
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i2c1_pins: i2c1-pins {
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pinmux = <APPLE_PINMUX(182, 1)>,
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<APPLE_PINMUX(181, 1)>;
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};
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i2c2_pins: i2c2-pins {
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pinmux = <APPLE_PINMUX(4, 1)>,
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<APPLE_PINMUX(3, 1)>;
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};
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i2c3_pins: i2c3-pins {
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pinmux = <APPLE_PINMUX(184, 1)>,
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<APPLE_PINMUX(183, 1)>;
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};
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};
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pinctrl_aop: pinctrl@2340f0000 {
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compatible = "apple,t8015-pinctrl", "apple,pinctrl";
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reg = <0x2 0x340f0000 0x0 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aop 0 0 49>;
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apple,npins = <49>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 135 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 136 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 138 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 139 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 140 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 141 IRQ_TYPE_LEVEL_HIGH>;
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};
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spmi: spmi@235180700 {
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compatible = "apple,t8015-spmi", "apple,t8103-spmi";
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reg = <0x2 0x35180700 0x0 0x100>;
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#address-cells = <2>;
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#size-cells = <0>;
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};
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pinctrl_nub: pinctrl@2351f0000 {
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compatible = "apple,t8015-pinctrl", "apple,pinctrl";
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reg = <0x2 0x351f0000 0x0 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_nub 0 0 8>;
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apple,npins = <8>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 168 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 169 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 170 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmgr_mini: power-management@235200000 {
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compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x2 0x35200000 0 0x84000>;
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};
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wdt: watchdog@2352b0000 {
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compatible = "apple,t8015-wdt", "apple,wdt";
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reg = <0x2 0x352b0000 0x0 0x4000>;
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clocks = <&clkref>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 172 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_smc: pinctrl@236024000 {
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compatible = "apple,t8015-pinctrl", "apple,pinctrl";
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reg = <0x2 0x36024000 0x0 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_smc 0 0 6>;
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apple,npins = <6>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH>;
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/*
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* SMC is not yet supported and accessing this pinctrl while SMC is
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* suspended results in a hang.
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*/
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status = "disabled";
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};
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ans_mbox: mbox@257008000 {
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compatible = "apple,t8015-asc-mailbox";
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reg = <0x2 0x57008000 0x0 0x4000>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 265 IRQ_TYPE_LEVEL_HIGH>,
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|
<AIC_IRQ 266 IRQ_TYPE_LEVEL_HIGH>,
|
|
<AIC_IRQ 267 IRQ_TYPE_LEVEL_HIGH>,
|
|
<AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "send-empty", "send-not-empty",
|
|
"recv-empty", "recv-not-empty";
|
|
#mbox-cells = <0>;
|
|
power-domains = <&ps_ans2>;
|
|
};
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|
|
|
sart: iommu@259c50000 {
|
|
compatible = "apple,t8015-sart";
|
|
reg = <0x2 0x59c50000 0x0 0x10000>;
|
|
power-domains = <&ps_ans2>;
|
|
};
|
|
|
|
nvme@259cc0000 {
|
|
compatible = "apple,t8015-nvme-ans2";
|
|
reg = <0x2 0x59cc0000 0x0 0x40000>,
|
|
<0x2 0x59d20000 0x0 0x2000>;
|
|
reg-names = "nvme", "ans";
|
|
interrupt-parent = <&aic>;
|
|
interrupts = <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>;
|
|
mboxes = <&ans_mbox>;
|
|
apple,sart = <&sart>;
|
|
power-domains = <&ps_ans2>, <&ps_pcie>;
|
|
power-domain-names = "ans", "apcie0";
|
|
resets = <&ps_ans2>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupt-parent = <&aic>;
|
|
interrupt-names = "phys", "virt";
|
|
/* Note that A11 doesn't actually have a hypervisor (EL2 is not implemented). */
|
|
interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
|
|
<AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
#include "t8015-pmgr.dtsi"
|