787 lines
18 KiB
Plaintext
787 lines
18 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright 2024 TechNexion Ltd.
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*
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* Author: Ray Chang <ray.chang@technexion.com>
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*/
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#include "imx8mp.dtsi"
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/ {
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chosen {
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stdout-path = &uart2;
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};
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i2c_0: i2c {
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compatible = "i2c-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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pinctrl-0 = <&pinctrl_i2c_brd_conf>;
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pinctrl-names = "default";
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scl-gpios = <&gpio4 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio4 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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eeprom: eeprom@53 {
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compatible = "atmel,24c02";
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reg = <0x53>;
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pagesize = <16>;
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};
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};
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memory@40000000 {
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reg = <0x0 0x40000000 0 0xc0000000>,
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<0x1 0x00000000 0 0xc0000000>;
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device_type = "memory";
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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off-on-delay-us = <12000>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "VSD_3V3";
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startup-delay-us = <100>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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rfkill {
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compatible = "rfkill-gpio";
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name = "rfkill";
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pinctrl-0 = <&pinctrl_bt_ctrl>;
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pinctrl-names = "default";
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radio-type = "bluetooth";
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shutdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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};
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wl_reg_on: regulator-wl-reg-on {
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compatible = "regulator-fixed";
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off-on-delay-us = <20000>;
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pinctrl-0 = <&pinctrl_wifi_ctrl>;
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pinctrl-names = "default";
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "WL_REG_ON";
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startup-delay-us = <100>;
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gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&A53_0 {
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cpu-supply = <®_arm>;
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};
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&A53_1 {
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cpu-supply = <®_arm>;
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};
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&A53_2 {
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cpu-supply = <®_arm>;
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};
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&A53_3 {
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cpu-supply = <®_arm>;
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};
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&ecspi1 {
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#address-cells = <1>;
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#size-cells = <0>;
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cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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num-cs = <1>;
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pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
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pinctrl-names = "default";
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};
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&eqos {
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phy-handle = <ðphy0>;
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phy-mode = "rgmii-id";
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pinctrl-0 = <&pinctrl_eqos>;
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pinctrl-names = "default";
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snps,force_thresh_dma_mode;
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snps,mtl-rx-config = <&mtl_rx_setup>;
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snps,mtl-tx-config = <&mtl_tx_setup>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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eee-broken-1000t;
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reset-assert-us = <35000>;
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reset-deassert-us = <75000>;
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reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
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realtek,clkout-disable;
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};
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};
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mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <5>;
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queue0 {
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snps,dcb-algorithm;
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snps,map-to-dma-channel = <0>;
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snps,priority = <0x1>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,map-to-dma-channel = <1>;
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snps,priority = <0x2>;
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};
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queue2 {
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snps,dcb-algorithm;
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snps,map-to-dma-channel = <2>;
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snps,priority = <0x4>;
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};
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queue3 {
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snps,dcb-algorithm;
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snps,map-to-dma-channel = <3>;
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snps,priority = <0x8>;
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};
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queue4 {
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snps,dcb-algorithm;
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snps,map-to-dma-channel = <4>;
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snps,priority = <0xf0>;
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};
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};
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mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <5>;
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queue0 {
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,priority = <0x2>;
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};
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queue2 {
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snps,dcb-algorithm;
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snps,priority = <0x4>;
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};
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queue3 {
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snps,dcb-algorithm;
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snps,priority = <0x8>;
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};
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queue4 {
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snps,dcb-algorithm;
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snps,priority = <0xf0>;
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};
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};
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};
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&flexcan1 {
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pinctrl-0 = <&pinctrl_flexcan1>;
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pinctrl-names = "default";
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};
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&flexcan2 {
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pinctrl-0 = <&pinctrl_flexcan2>;
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pinctrl-names = "default";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-names = "default";
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status = "okay";
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pmic: pmic@25 {
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compatible = "nxp,pca9450c";
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reg = <0x25>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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regulators {
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BUCK1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1000000>;
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regulator-min-microvolt = <720000>;
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regulator-name = "BUCK1";
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regulator-ramp-delay = <3125>;
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};
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reg_arm: BUCK2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1025000>;
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regulator-min-microvolt = <720000>;
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regulator-name = "BUCK2";
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regulator-ramp-delay = <3125>;
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nxp,dvs-run-voltage = <950000>;
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nxp,dvs-standby-voltage = <850000>;
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};
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BUCK4 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <3600000>;
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regulator-min-microvolt = <3000000>;
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regulator-name = "BUCK4";
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};
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reg_buck5: BUCK5 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1950000>;
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regulator-min-microvolt = <1650000>;
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regulator-name = "BUCK5";
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};
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BUCK6 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1155000>;
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regulator-min-microvolt = <1045000>;
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regulator-name = "BUCK6";
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};
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LDO1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1950000>;
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regulator-min-microvolt = <1650000>;
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regulator-name = "LDO1";
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};
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LDO3 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1890000>;
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regulator-min-microvolt = <1710000>;
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regulator-name = "LDO3";
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};
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LDO5 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "LDO5";
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};
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};
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};
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};
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&i2c2 {
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/* I2C_B on EDMG */
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clock-frequency = <400000>;
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-names = "default";
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-0 = <&pinctrl_i2c3>;
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pinctrl-names = "default";
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};
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&i2c4 {
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/* I2C_A on EDMG */
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clock-frequency = <100000>;
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pinctrl-0 = <&pinctrl_i2c4>;
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pinctrl-names = "default";
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};
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&i2c5 {
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/* I2C_C on EDMG */
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clock-frequency = <400000>;
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pinctrl-0 = <&pinctrl_i2c5>;
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pinctrl-names = "default";
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};
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&pcie {
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pinctrl-0 = <&pinctrl_pcie>;
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pinctrl-names = "default";
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reset-gpio = <&gpio1 1 GPIO_ACTIVE_LOW>;
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};
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&pwm1 {
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pinctrl-0 = <&pinctrl_pwm1>;
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pinctrl-names = "default";
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status = "okay";
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};
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&pwm2 {
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pinctrl-0 = <&pinctrl_pwm2>;
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pinctrl-names = "default";
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status = "okay";
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};
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&pwm3 {
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pinctrl-0 = <&pinctrl_pwm3>;
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pinctrl-names = "default";
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status = "okay";
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};
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&pwm4 {
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pinctrl-0 = <&pinctrl_pwm4>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sai2 {
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/* AUD_B on EDMG */
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assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
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assigned-clock-rates = <12288000>;
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assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
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pinctrl-0 = <&pinctrl_sai2>;
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pinctrl-names = "default";
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fsl,sai-mclk-direction-output;
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status = "okay";
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};
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&sai3 {
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/* AUD_A on EDMG */
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assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
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assigned-clock-rates = <12288000>;
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assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
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pinctrl-0 = <&pinctrl_sai3>;
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pinctrl-names = "default";
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fsl,sai-mclk-direction-output;
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status = "okay";
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};
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&uart1 {
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/* BT */
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assigned-clocks = <&clk IMX8MP_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
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pinctrl-0 = <&pinctrl_uart1>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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&uart2 {
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/* UART_A on EDMG, console */
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pinctrl-0 = <&pinctrl_uart2>;
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pinctrl-names = "default";
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status = "okay";
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};
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&uart3 {
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/* UART_C on EDMG */
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assigned-clocks = <&clk IMX8MP_CLK_UART3>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
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pinctrl-0 = <&pinctrl_uart3>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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&uart4 {
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/* UART_B on EDMG */
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assigned-clocks = <&clk IMX8MP_CLK_UART4>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
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pinctrl-0 = <&pinctrl_uart4>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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&usdhc1 {
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/* WIFI SDIO */
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assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
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assigned-clock-rates = <200000000>;
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bus-width = <4>;
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keep-power-in-suspend;
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non-removable;
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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vmmc-supply = <&wl_reg_on>;
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status = "okay";
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};
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&usdhc2 {
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/* SD card on baseboard */
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assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
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assigned-clock-rates = <400000000>;
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bus-width = <4>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&usdhc3 {
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/* eMMC on SOM */
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assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
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assigned-clock-rates = <400000000>;
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bus-width = <8>;
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non-removable;
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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status = "okay";
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};
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&wdog1 {
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pinctrl-0 = <&pinctrl_wdog>;
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pinctrl-names = "default";
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl-names = "default";
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pinctrl_bt_ctrl: bt-ctrlgrp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x41 /* BT_REG_ON */
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MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x41 /* BT_WAKE_HOST */
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>;
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};
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pinctrl_ecspi1_cs: ecspi1csgrp {
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fsl,pins = <
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MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40000
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>;
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};
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82
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MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82
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MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82
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>;
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};
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
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MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x23
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MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
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MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
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MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
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MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
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MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
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MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
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MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
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MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
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MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
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MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
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MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
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MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
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MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x19
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MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
|
|
MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan2: flexcan2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
|
|
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
|
|
>;
|
|
};
|
|
|
|
pinctrl_hog: hoggrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001a3
|
|
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001a3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001a3
|
|
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001a3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
|
|
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c4: i2c4grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
|
|
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c5: i2c5grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001a3
|
|
MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001a3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c_brd_conf: i2cbrdconfgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c3 /* BRD_CONF_SCL, bitbang */
|
|
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c3 /* BRD_CONF_SDA, bitbang */
|
|
>;
|
|
};
|
|
|
|
pinctrl_pcie: pciegrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x41 /* PCIE CLKREQ */
|
|
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x41 /* PCIE WAKE */
|
|
MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x41 /* PCIE RST */
|
|
>;
|
|
};
|
|
|
|
pinctrl_pmic: pmicirqgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm1: pwm1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm2: pwm2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm3: pwm3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm4: pwm4grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai2: sai2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6
|
|
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
|
|
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
|
|
MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
|
|
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai3: sai3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
|
|
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
|
|
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
|
|
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
|
|
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
|
|
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
|
|
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
|
|
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
|
|
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
|
|
MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x140
|
|
MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3: uart3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140
|
|
MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140
|
|
MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140
|
|
MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart4: uart4grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x140
|
|
MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x140
|
|
MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x140
|
|
MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
|
|
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
|
|
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
|
|
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
|
|
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
|
|
>;
|
|
};
|
|
|
|
pinctrl_wifi_ctrl: wifi-ctrlgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x41 /* WL_REG_ON */
|
|
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x41 /* WL_WAKE_HOST */
|
|
>;
|
|
};
|
|
};
|