899 lines
21 KiB
Plaintext
899 lines
21 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright 2021-2024 NXP
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*
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* Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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* Ciprian Costea <ciprianmarian.costea@nxp.com>
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* Andra-Teodora Ilie <andra.ilie@nxp.com>
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "nxp,s32g3";
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interrupt-parent = <&gic>;
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x102>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x103>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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};
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firmware {
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scmi: scmi {
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compatible = "arm,scmi-smc";
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shmem = <&scmi_shmem>;
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arm,smc-id = <0xc20000fe>;
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#address-cells = <1>;
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#size-cells = <0>;
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dfs: protocol@13 {
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reg = <0x13>;
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#clock-cells = <1>;
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};
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clks: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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scmi_shmem: shm@d0000000 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0xd0000000 0x0 0x80>;
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no-map;
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};
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0x80000000>;
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rtc0: rtc@40060000 {
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compatible = "nxp,s32g3-rtc",
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"nxp,s32g2-rtc";
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reg = <0x40060000 0x1000>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 54>, <&clks 55>;
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clock-names = "ipg", "source0";
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};
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pinctrl: pinctrl@4009c240 {
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compatible = "nxp,s32g2-siul2-pinctrl";
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/* MSCR0-MSCR101 registers on siul2_0 */
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reg = <0x4009c240 0x198>,
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/* MSCR112-MSCR122 registers on siul2_1 */
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<0x44010400 0x2c>,
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/* MSCR144-MSCR190 registers on siul2_1 */
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<0x44010480 0xbc>,
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/* IMCR0-IMCR83 registers on siul2_0 */
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<0x4009ca40 0x150>,
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/* IMCR119-IMCR397 registers on siul2_1 */
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<0x44010c1c 0x45c>,
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/* IMCR430-IMCR495 registers on siul2_1 */
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<0x440110f8 0x108>;
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jtag_pins: jtag-pins {
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jtag-grp0 {
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pinmux = <0x0>;
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input-enable;
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bias-pull-up;
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slew-rate = <166>;
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};
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jtag-grp1 {
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pinmux = <0x11>;
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slew-rate = <166>;
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};
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jtag-grp2 {
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pinmux = <0x40>;
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input-enable;
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bias-pull-down;
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slew-rate = <166>;
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};
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jtag-grp3 {
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pinmux = <0x23c0>,
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<0x23d0>,
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<0x2320>;
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};
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jtag-grp4 {
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pinmux = <0x51>;
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input-enable;
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bias-pull-up;
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slew-rate = <166>;
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};
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};
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pinctrl_usdhc0: usdhc0grp-pins {
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usdhc0-grp0 {
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pinmux = <0x2e1>,
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<0x381>;
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output-enable;
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bias-pull-down;
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slew-rate = <150>;
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};
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usdhc0-grp1 {
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pinmux = <0x2f1>,
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<0x301>,
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<0x311>,
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<0x321>,
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<0x331>,
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<0x341>,
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<0x351>,
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<0x361>,
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<0x371>;
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output-enable;
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input-enable;
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bias-pull-up;
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slew-rate = <150>;
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};
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usdhc0-grp2 {
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pinmux = <0x391>;
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output-enable;
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slew-rate = <150>;
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};
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usdhc0-grp3 {
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pinmux = <0x3a0>;
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input-enable;
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slew-rate = <150>;
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};
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usdhc0-grp4 {
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pinmux = <0x2032>,
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<0x2042>,
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<0x2052>,
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<0x2062>,
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<0x2072>,
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<0x2082>,
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<0x2092>,
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<0x20a2>,
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<0x20b2>,
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<0x20c2>;
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};
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};
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pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {
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usdhc0-100mhz-grp0 {
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pinmux = <0x2e1>,
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<0x381>;
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output-enable;
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bias-pull-down;
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slew-rate = <150>;
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};
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usdhc0-100mhz-grp1 {
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pinmux = <0x2f1>,
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<0x301>,
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<0x311>,
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<0x321>,
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<0x331>,
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<0x341>,
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<0x351>,
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<0x361>,
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<0x371>;
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output-enable;
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input-enable;
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bias-pull-up;
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slew-rate = <150>;
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};
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usdhc0-100mhz-grp2 {
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pinmux = <0x391>;
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output-enable;
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slew-rate = <150>;
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};
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usdhc0-100mhz-grp3 {
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pinmux = <0x3a0>;
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input-enable;
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slew-rate = <150>;
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};
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usdhc0-100mhz-grp4 {
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pinmux = <0x2032>,
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<0x2042>,
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<0x2052>,
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<0x2062>,
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<0x2072>,
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<0x2082>,
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<0x2092>,
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<0x20a2>,
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<0x20b2>,
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<0x20c2>;
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};
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};
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pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {
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usdhc0-200mhz-grp0 {
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pinmux = <0x2e1>,
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<0x381>;
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output-enable;
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bias-pull-down;
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slew-rate = <208>;
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};
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usdhc0-200mhz-grp1 {
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pinmux = <0x2f1>,
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<0x301>,
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<0x311>,
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<0x321>,
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<0x331>,
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<0x341>,
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<0x351>,
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<0x361>,
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<0x371>;
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output-enable;
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input-enable;
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bias-pull-up;
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slew-rate = <208>;
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};
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usdhc0-200mhz-grp2 {
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pinmux = <0x391>;
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output-enable;
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slew-rate = <208>;
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};
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usdhc0-200mhz-grp3 {
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pinmux = <0x3a0>;
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input-enable;
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slew-rate = <208>;
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};
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usdhc0-200mhz-grp4 {
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pinmux = <0x2032>,
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<0x2042>,
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<0x2052>,
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<0x2062>,
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<0x2072>,
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<0x2082>,
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<0x2092>,
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<0x20a2>,
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<0x20b2>,
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<0x20c2>;
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};
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};
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};
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ocotp: nvmem@400a4000 {
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compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";
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reg = <0x400a4000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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swt0: watchdog@40100000 {
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compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
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reg = <0x40100000 0x1000>;
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clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
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clock-names = "counter", "module", "register";
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status = "disabled";
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};
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swt1: watchdog@40104000 {
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compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
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reg = <0x40104000 0x1000>;
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clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
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clock-names = "counter", "module", "register";
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status = "disabled";
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};
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swt2: watchdog@40108000 {
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compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
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reg = <0x40108000 0x1000>;
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clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
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clock-names = "counter", "module", "register";
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status = "disabled";
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};
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swt3: watchdog@4010c000 {
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compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
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reg = <0x4010c000 0x1000>;
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clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
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clock-names = "counter", "module", "register";
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status = "disabled";
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};
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stm0: timer@4011c000 {
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compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
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reg = <0x4011c000 0x3000>;
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clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
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clock-names = "counter", "module", "register";
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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stm1: timer@40120000 {
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compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
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reg = <0x40120000 0x3000>;
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clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
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clock-names = "counter", "module", "register";
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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stm2: timer@40124000 {
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compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
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reg = <0x40124000 0x3000>;
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clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
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clock-names = "counter", "module", "register";
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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stm3: timer@40128000 {
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compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
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reg = <0x40128000 0x3000>;
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clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
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clock-names = "counter", "module", "register";
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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edma0: dma-controller@40144000 {
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compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
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reg = <0x40144000 0x24000>,
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<0x4012c000 0x3000>,
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<0x40130000 0x3000>;
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#dma-cells = <2>;
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dma-channels = <32>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tx-0-15",
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"tx-16-31",
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"err";
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clocks = <&clks 63>, <&clks 64>;
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clock-names = "dmamux0", "dmamux1";
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};
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can0: can@401b4000 {
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compatible = "nxp,s32g3-flexcan",
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"nxp,s32g2-flexcan";
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reg = <0x401b4000 0xa000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mb-0", "state", "berr", "mb-1";
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clocks = <&clks 9>, <&clks 11>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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can1: can@401be000 {
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compatible = "nxp,s32g3-flexcan",
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"nxp,s32g2-flexcan";
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reg = <0x401be000 0xa000>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mb-0", "state", "berr", "mb-1";
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clocks = <&clks 9>, <&clks 11>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart0: serial@401c8000 {
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compatible = "nxp,s32g3-linflexuart",
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"fsl,s32v234-linflexuart";
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reg = <0x401c8000 0x3000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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uart1: serial@401cc000 {
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compatible = "nxp,s32g3-linflexuart",
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"fsl,s32v234-linflexuart";
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reg = <0x401cc000 0x3000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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usbmisc: usbmisc@44064200 {
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#index-cells = <1>;
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compatible = "nxp,s32g3-usbmisc";
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reg = <0x44064200 0x200>;
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};
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usbotg: usb@44064000 {
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compatible = "nxp,s32g3-usb", "nxp,s32g2-usb";
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reg = <0x44064000 0x200>;
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interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, /* OTG Core */
|
|
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; /* OTG Wakeup */
|
|
clocks = <&clks 94>, <&clks 95>;
|
|
fsl,usbmisc = <&usbmisc 0>;
|
|
ahb-burst-config = <0x3>;
|
|
tx-burst-size-dword = <0x10>;
|
|
rx-burst-size-dword = <0x10>;
|
|
phy_type = "ulpi";
|
|
dr_mode = "host";
|
|
maximum-speed = "high-speed";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@401d4000 {
|
|
compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
|
|
reg = <0x401d4000 0x1000>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks 26>;
|
|
clock-names = "dspi";
|
|
spi-num-chipselects = <8>;
|
|
bus-num = <0>;
|
|
dmas = <&edma0 0 7>, <&edma0 0 8>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@401d8000 {
|
|
compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
|
|
reg = <0x401d8000 0x1000>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks 26>;
|
|
clock-names = "dspi";
|
|
spi-num-chipselects = <5>;
|
|
bus-num = <1>;
|
|
dmas = <&edma0 0 10>, <&edma0 0 11>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@401dc000 {
|
|
compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
|
|
reg = <0x401dc000 0x1000>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks 26>;
|
|
clock-names = "dspi";
|
|
spi-num-chipselects = <5>;
|
|
bus-num = <2>;
|
|
dmas = <&edma0 0 13>, <&edma0 0 14>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@401e4000 {
|
|
compatible = "nxp,s32g3-i2c",
|
|
"nxp,s32g2-i2c";
|
|
reg = <0x401e4000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks 40>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@401e8000 {
|
|
compatible = "nxp,s32g3-i2c",
|
|
"nxp,s32g2-i2c";
|
|
reg = <0x401e8000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks 40>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@401ec000 {
|
|
compatible = "nxp,s32g3-i2c",
|
|
"nxp,s32g2-i2c";
|
|
reg = <0x401ec000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks 40>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
swt4: watchdog@40200000 {
|
|
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
|
|
reg = <0x40200000 0x1000>;
|
|
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
|
|
clock-names = "counter", "module", "register";
|
|
status = "disabled";
|
|
};
|
|
|
|
swt5: watchdog@40204000 {
|
|
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
|
|
reg = <0x40204000 0x1000>;
|
|
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
|
|
clock-names = "counter", "module", "register";
|
|
status = "disabled";
|
|
};
|
|
|
|
swt6: watchdog@40208000 {
|
|
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
|
|
reg = <0x40208000 0x1000>;
|
|
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
|
|
clock-names = "counter", "module", "register";
|
|
status = "disabled";
|
|
};
|
|
|
|
swt7: watchdog@4020C000 {
|
|
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
|
|
reg = <0x4020C000 0x1000>;
|
|
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
|
|
clock-names = "counter", "module", "register";
|
|
status = "disabled";
|
|
};
|
|
|
|
stm4: timer@4021c000 {
|
|
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
|
|
reg = <0x4021c000 0x3000>;
|
|
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
|
|
clock-names = "counter", "module", "register";
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
stm5: timer@40220000 {
|
|
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
|
|
reg = <0x40220000 0x3000>;
|
|
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
|
|
clock-names = "counter", "module", "register";
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
stm6: timer@40224000 {
|
|
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
|
|
reg = <0x40224000 0x3000>;
|
|
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
|
|
clock-names = "counter", "module", "register";
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
edma1: dma-controller@40244000 {
|
|
compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
|
|
reg = <0x40244000 0x24000>,
|
|
<0x4022c000 0x3000>,
|
|
<0x40230000 0x3000>;
|
|
#dma-cells = <2>;
|
|
dma-channels = <32>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tx-0-15",
|
|
"tx-16-31",
|
|
"err";
|
|
clocks = <&clks 63>, <&clks 64>;
|
|
clock-names = "dmamux0", "dmamux1";
|
|
};
|
|
|
|
can2: can@402a8000 {
|
|
compatible = "nxp,s32g3-flexcan",
|
|
"nxp,s32g2-flexcan";
|
|
reg = <0x402a8000 0xa000>;
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mb-0", "state", "berr", "mb-1";
|
|
clocks = <&clks 9>, <&clks 11>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
can3: can@402b2000 {
|
|
compatible = "nxp,s32g3-flexcan",
|
|
"nxp,s32g2-flexcan";
|
|
reg = <0x402b2000 0xa000>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mb-0", "state", "berr", "mb-1";
|
|
clocks = <&clks 9>, <&clks 11>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@402bc000 {
|
|
compatible = "nxp,s32g3-linflexuart",
|
|
"fsl,s32v234-linflexuart";
|
|
reg = <0x402bc000 0x3000>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@402c8000 {
|
|
compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
|
|
reg = <0x402c8000 0x1000>;
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks 26>;
|
|
clock-names = "dspi";
|
|
spi-num-chipselects = <5>;
|
|
bus-num = <3>;
|
|
dmas = <&edma0 1 7>, <&edma0 1 8>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi4: spi@402cc000 {
|
|
compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
|
|
reg = <0x402cc000 0x1000>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks 26>;
|
|
clock-names = "dspi";
|
|
spi-num-chipselects = <5>;
|
|
bus-num = <4>;
|
|
dmas = <&edma0 1 10>, <&edma0 1 11>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi5: spi@402d0000 {
|
|
compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
|
|
reg = <0x402d0000 0x1000>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks 26>;
|
|
clock-names = "dspi";
|
|
spi-num-chipselects = <5>;
|
|
bus-num = <5>;
|
|
dmas = <&edma0 1 13>, <&edma0 1 14>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@402d8000 {
|
|
compatible = "nxp,s32g3-i2c",
|
|
"nxp,s32g2-i2c";
|
|
reg = <0x402d8000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks 40>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@402dc000 {
|
|
compatible = "nxp,s32g3-i2c",
|
|
"nxp,s32g2-i2c";
|
|
reg = <0x402dc000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks 40>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc0: mmc@402f0000 {
|
|
compatible = "nxp,s32g3-usdhc",
|
|
"nxp,s32g2-usdhc";
|
|
reg = <0x402f0000 0x1000>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks 32>,
|
|
<&clks 31>,
|
|
<&clks 33>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
swt8: watchdog@40500000 {
|
|
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
|
|
reg = <40500000 0x1000>;
|
|
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
|
|
clock-names = "counter", "module", "register";
|
|
status = "disabled";
|
|
};
|
|
|
|
swt9: watchdog@40504000 {
|
|
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
|
|
reg = <0x40504000 0x1000>;
|
|
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
|
|
clock-names = "counter", "module", "register";
|
|
status = "disabled";
|
|
};
|
|
|
|
swt10: watchdog@40508000 {
|
|
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
|
|
reg = <0x40508000 0x1000>;
|
|
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
|
|
clock-names = "counter", "module", "register";
|
|
status = "disabled";
|
|
};
|
|
|
|
swt11: watchdog@4050c000 {
|
|
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
|
|
reg = <0x4050c000 0x1000>;
|
|
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
|
|
clock-names = "counter", "module", "register";
|
|
status = "disabled";
|
|
};
|
|
|
|
stm8: timer@40520000 {
|
|
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
|
|
reg = <0x40520000 0x3000>;
|
|
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
|
|
clock-names = "counter", "module", "register";
|
|
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
stm9: timer@40524000 {
|
|
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
|
|
reg = <0x40524000 0x3000>;
|
|
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
|
|
clock-names = "counter", "module", "register";
|
|
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
stm10: timer@40528000 {
|
|
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
|
|
reg = <0x40528000 0x3000>;
|
|
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
|
|
clock-names = "counter", "module", "register";
|
|
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
stm11: timer@4052c000 {
|
|
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
|
|
reg = <0x4052c000 0x3000>;
|
|
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
|
|
clock-names = "counter", "module", "register";
|
|
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@50800000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
reg = <0x50800000 0x10000>,
|
|
<0x50900000 0x200000>,
|
|
<0x50400000 0x2000>,
|
|
<0x50410000 0x2000>,
|
|
<0x50420000 0x2000>;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* phys */
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* virt */
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */
|
|
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */
|
|
arm,no-tick-in-suspend;
|
|
};
|
|
};
|