151 lines
4.1 KiB
C
151 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2025 MediaTek Inc.
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* Guangjie Song <guangjie.song@mediatek.com>
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* Copyright (c) 2025 Collabora Ltd.
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* Laura Nao <laura.nao@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8196-clock.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-pll.h"
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#define MFGPLL_CON0 0x008
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#define MFGPLL_CON1 0x00c
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#define MFGPLL_CON2 0x010
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#define MFGPLL_CON3 0x014
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#define MFGPLL_SC0_CON0 0x008
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#define MFGPLL_SC0_CON1 0x00c
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#define MFGPLL_SC0_CON2 0x010
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#define MFGPLL_SC0_CON3 0x014
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#define MFGPLL_SC1_CON0 0x008
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#define MFGPLL_SC1_CON1 0x00c
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#define MFGPLL_SC1_CON2 0x010
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#define MFGPLL_SC1_CON3 0x014
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#define MT8196_PLL_FMAX (3800UL * MHZ)
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#define MT8196_PLL_FMIN (1500UL * MHZ)
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#define MT8196_INTEGER_BITS 8
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#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pll_en_bit, \
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_flags, _rst_bar_mask, \
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_pd_reg, _pd_shift, _tuner_reg, \
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_tuner_en_reg, _tuner_en_bit, \
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_pcw_reg, _pcw_shift, _pcwbits) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.en_reg = _en_reg, \
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.en_mask = _en_mask, \
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.pll_en_bit = _pll_en_bit, \
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.flags = _flags, \
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.rst_bar_mask = _rst_bar_mask, \
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.fmax = MT8196_PLL_FMAX, \
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.fmin = MT8196_PLL_FMIN, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.tuner_en_reg = _tuner_en_reg, \
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.tuner_en_bit = _tuner_en_bit, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.pcwbits = _pcwbits, \
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.pcwibits = MT8196_INTEGER_BITS, \
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}
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static const struct mtk_pll_data mfg_ao_plls[] = {
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PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0, 0,
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BIT(0), MFGPLL_CON1, 24, 0, 0, 0,
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MFGPLL_CON1, 0, 22),
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};
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static const struct mtk_pll_data mfgsc0_ao_plls[] = {
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PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0,
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MFGPLL_SC0_CON0, 0, 0, 0, BIT(0), MFGPLL_SC0_CON1, 24, 0, 0, 0,
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MFGPLL_SC0_CON1, 0, 22),
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};
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static const struct mtk_pll_data mfgsc1_ao_plls[] = {
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PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0,
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MFGPLL_SC1_CON0, 0, 0, 0, BIT(0), MFGPLL_SC1_CON1, 24, 0, 0, 0,
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MFGPLL_SC1_CON1, 0, 22),
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};
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static const struct of_device_id of_match_clk_mt8196_mfg[] = {
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{ .compatible = "mediatek,mt8196-mfgpll-pll-ctrl",
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.data = &mfg_ao_plls },
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{ .compatible = "mediatek,mt8196-mfgpll-sc0-pll-ctrl",
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.data = &mfgsc0_ao_plls },
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{ .compatible = "mediatek,mt8196-mfgpll-sc1-pll-ctrl",
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.data = &mfgsc1_ao_plls },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mfg);
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static int clk_mt8196_mfg_probe(struct platform_device *pdev)
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{
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const struct mtk_pll_data *plls;
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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const int num_plls = 1;
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int r;
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plls = of_device_get_match_data(&pdev->dev);
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if (!plls)
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return -EINVAL;
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clk_data = mtk_alloc_clk_data(num_plls);
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if (!clk_data)
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return -ENOMEM;
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r = mtk_clk_register_plls(node, plls, num_plls, clk_data);
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if (r)
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goto free_clk_data;
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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goto unregister_plls;
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platform_set_drvdata(pdev, clk_data);
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return r;
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unregister_plls:
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mtk_clk_unregister_plls(plls, num_plls, clk_data);
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free_clk_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static void clk_mt8196_mfg_remove(struct platform_device *pdev)
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{
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const struct mtk_pll_data *plls = of_device_get_match_data(&pdev->dev);
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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struct device_node *node = pdev->dev.of_node;
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of_clk_del_provider(node);
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mtk_clk_unregister_plls(plls, 1, clk_data);
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mtk_free_clk_data(clk_data);
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}
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static struct platform_driver clk_mt8196_mfg_drv = {
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.probe = clk_mt8196_mfg_probe,
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.remove = clk_mt8196_mfg_remove,
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.driver = {
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.name = "clk-mt8196-mfg",
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.of_match_table = of_match_clk_mt8196_mfg,
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},
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};
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module_platform_driver(clk_mt8196_mfg_drv);
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MODULE_DESCRIPTION("MediaTek MT8196 GPU mfg clocks driver");
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MODULE_LICENSE("GPL");
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