505 lines
17 KiB
C
505 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2025 Intel Corporation */
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#ifndef ADF_GEN6_RAS_H_
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#define ADF_GEN6_RAS_H_
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#include <linux/bits.h>
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struct adf_ras_ops;
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/* Error source registers */
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#define ADF_GEN6_ERRSOU0 0x41A200
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#define ADF_GEN6_ERRSOU1 0x41A204
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#define ADF_GEN6_ERRSOU2 0x41A208
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#define ADF_GEN6_ERRSOU3 0x41A20C
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/* Error source mask registers */
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#define ADF_GEN6_ERRMSK0 0x41A210
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#define ADF_GEN6_ERRMSK1 0x41A214
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#define ADF_GEN6_ERRMSK2 0x41A218
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#define ADF_GEN6_ERRMSK3 0x41A21C
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/* ERRSOU0 Correctable error mask */
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#define ADF_GEN6_ERRSOU0_MASK BIT(0)
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#define ADF_GEN6_ERRSOU1_CPP0_MEUNC_BIT BIT(0)
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#define ADF_GEN6_ERRSOU1_CPP_CMDPARERR_BIT BIT(1)
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#define ADF_GEN6_ERRSOU1_RIMEM_PARERR_STS_BIT BIT(2)
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#define ADF_GEN6_ERRSOU1_TIMEM_PARERR_STS_BIT BIT(3)
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#define ADF_GEN6_ERRSOU1_SFICMD_PARERR_BIT BIT(4)
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#define ADF_GEN6_ERRSOU1_MASK ( \
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(ADF_GEN6_ERRSOU1_CPP0_MEUNC_BIT) | \
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(ADF_GEN6_ERRSOU1_CPP_CMDPARERR_BIT) | \
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(ADF_GEN6_ERRSOU1_RIMEM_PARERR_STS_BIT) | \
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(ADF_GEN6_ERRSOU1_TIMEM_PARERR_STS_BIT) | \
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(ADF_GEN6_ERRSOU1_SFICMD_PARERR_BIT))
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#define ADF_GEN6_ERRMSK1_CPP0_MEUNC_BIT BIT(0)
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#define ADF_GEN6_ERRMSK1_CPP_CMDPARERR_BIT BIT(1)
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#define ADF_GEN6_ERRMSK1_RIMEM_PARERR_STS_BIT BIT(2)
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#define ADF_GEN6_ERRMSK1_TIMEM_PARERR_STS_BIT BIT(3)
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#define ADF_GEN6_ERRMSK1_IOSFCMD_PARERR_BIT BIT(4)
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#define ADF_GEN6_ERRMSK1_MASK ( \
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(ADF_GEN6_ERRMSK1_CPP0_MEUNC_BIT) | \
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(ADF_GEN6_ERRMSK1_CPP_CMDPARERR_BIT) | \
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(ADF_GEN6_ERRMSK1_RIMEM_PARERR_STS_BIT) | \
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(ADF_GEN6_ERRMSK1_TIMEM_PARERR_STS_BIT) | \
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(ADF_GEN6_ERRMSK1_IOSFCMD_PARERR_BIT))
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/* HI AE Uncorrectable error log */
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#define ADF_GEN6_HIAEUNCERRLOG_CPP0 0x41A300
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/* HI AE Uncorrectable error log enable */
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#define ADF_GEN6_HIAEUNCERRLOGENABLE_CPP0 0x41A320
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/* HI AE Correctable error log */
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#define ADF_GEN6_HIAECORERRLOG_CPP0 0x41A308
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/* HI AE Correctable error log enable */
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#define ADF_GEN6_HIAECORERRLOGENABLE_CPP0 0x41A318
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/* HI CPP Agent Command parity error log */
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#define ADF_GEN6_HICPPAGENTCMDPARERRLOG 0x41A310
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/* HI CPP Agent command parity error logging enable */
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#define ADF_GEN6_HICPPAGENTCMDPARERRLOGENABLE 0x41A314
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#define ADF_6XXX_HICPPAGENTCMDPARERRLOG_MASK 0x1B
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/* RI Memory parity error status register */
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#define ADF_GEN6_RIMEM_PARERR_STS 0x41B128
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/* RI Memory parity error reporting enable */
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#define ADF_GEN6_RI_MEM_PAR_ERR_EN0 0x41B12C
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/*
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* RI Memory parity error mask
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* BIT(4) - ri_tlq_phdr parity error
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* BIT(5) - ri_tlq_pdata parity error
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* BIT(6) - ri_tlq_nphdr parity error
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* BIT(7) - ri_tlq_npdata parity error
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* BIT(8) - ri_tlq_cplhdr parity error
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* BIT(10) - BIT(13) - ri_tlq_cpldata[0:3] parity error
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* BIT(19) - ri_cds_cmd_fifo parity error
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* BIT(20) - ri_obc_ricpl_fifo parity error
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* BIT(21) - ri_obc_tiricpl_fifo parity error
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* BIT(22) - ri_obc_cppcpl_fifo parity error
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* BIT(23) - ri_obc_pendcpl_fifo parity error
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* BIT(24) - ri_cpp_cmd_fifo parity error
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* BIT(25) - ri_cds_ticmd_fifo parity error
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* BIT(26) - riti_cmd_fifo parity error
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* BIT(27) - ri_int_msixtbl parity error
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* BIT(28) - ri_int_imstbl parity error
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* BIT(30) - ri_kpt_fuses parity error
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*/
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#define ADF_GEN6_RIMEM_PARERR_FATAL_MASK \
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(BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | \
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BIT(7) | BIT(8) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | \
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BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27) | \
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BIT(28) | BIT(30))
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#define ADF_GEN6_RIMEM_PARERR_CERR_MASK \
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(BIT(10) | BIT(11) | BIT(12) | BIT(13))
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/* TI CI parity status */
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#define ADF_GEN6_TI_CI_PAR_STS 0x50060C
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/* TI CI parity reporting mask */
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#define ADF_GEN6_TI_CI_PAR_ERR_MASK 0x500608
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/*
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* TI CI parity status mask
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* BIT(0) - CdCmdQ_sts patiry error status
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* BIT(1) - CdDataQ_sts parity error status
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* BIT(3) - CPP_SkidQ_sts parity error status
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*/
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#define ADF_GEN6_TI_CI_PAR_STS_MASK \
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(BIT(0) | BIT(1) | BIT(3))
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/* TI PULLFUB parity status */
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#define ADF_GEN6_TI_PULL0FUB_PAR_STS 0x500618
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/* TI PULLFUB parity error reporting mask */
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#define ADF_GEN6_TI_PULL0FUB_PAR_ERR_MASK 0x500614
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/*
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* TI PULLFUB parity status mask
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* BIT(0) - TrnPullReqQ_sts parity status
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* BIT(1) - TrnSharedDataQ_sts parity status
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* BIT(2) - TrnPullReqDataQ_sts parity status
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* BIT(4) - CPP_CiPullReqQ_sts parity status
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* BIT(5) - CPP_TrnPullReqQ_sts parity status
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* BIT(6) - CPP_PullidQ_sts parity status
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* BIT(7) - CPP_WaitDataQ_sts parity status
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* BIT(8) - CPP_CdDataQ_sts parity status
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* BIT(9) - CPP_TrnDataQP0_sts parity status
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* BIT(10) - BIT(11) - CPP_TrnDataQRF[00:01]_sts parity status
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* BIT(12) - CPP_TrnDataQP1_sts parity status
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* BIT(13) - BIT(14) - CPP_TrnDataQRF[10:11]_sts parity status
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*/
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#define ADF_GEN6_TI_PULL0FUB_PAR_STS_MASK \
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(BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | \
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BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14))
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/* TI PUSHUB parity status */
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#define ADF_GEN6_TI_PUSHFUB_PAR_STS 0x500630
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/* TI PUSHFUB parity error reporting mask */
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#define ADF_GEN6_TI_PUSHFUB_PAR_ERR_MASK 0x50062C
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/*
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* TI PUSHUB parity status mask
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* BIT(0) - SbPushReqQ_sts parity status
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* BIT(1) - BIT(2) - SbPushDataQ[0:1]_sts parity status
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* BIT(4) - CPP_CdPushReqQ_sts parity status
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* BIT(5) - BIT(6) - CPP_CdPushDataQ[0:1]_sts parity status
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* BIT(7) - CPP_SbPushReqQ_sts parity status
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* BIT(8) - CPP_SbPushDataQP_sts parity status
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* BIT(9) - BIT(10) - CPP_SbPushDataQRF[0:1]_sts parity status
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*/
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#define ADF_GEN6_TI_PUSHFUB_PAR_STS_MASK \
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(BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | \
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BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10))
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/* TI CD parity status */
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#define ADF_GEN6_TI_CD_PAR_STS 0x50063C
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/* TI CD parity error mask */
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#define ADF_GEN6_TI_CD_PAR_ERR_MASK 0x500638
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/*
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* TI CD parity status mask
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* BIT(0) - BIT(15) - CtxMdRam[0:15]_sts parity status
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* BIT(16) - Leaf2ClusterRam_sts parity status
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* BIT(17) - BIT(18) - Ring2LeafRam[0:1]_sts parity status
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* BIT(19) - VirtualQ_sts parity status
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* BIT(20) - DtRdQ_sts parity status
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* BIT(21) - DtWrQ_sts parity status
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* BIT(22) - RiCmdQ_sts parity status
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* BIT(23) - BypassQ_sts parity status
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* BIT(24) - DtRdQ_sc_sts parity status
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* BIT(25) - DtWrQ_sc_sts parity status
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*/
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#define ADF_GEN6_TI_CD_PAR_STS_MASK \
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(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | \
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BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | \
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BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
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BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25))
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/* TI TRNSB parity status */
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#define ADF_GEN6_TI_TRNSB_PAR_STS 0x500648
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/* TI TRNSB parity error reporting mask */
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#define ADF_GEN6_TI_TRNSB_PAR_ERR_MASK 0x500644
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/*
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* TI TRNSB parity status mask
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* BIT(0) - TrnPHdrQP_sts parity status
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* BIT(1) - TrnPHdrQRF_sts parity status
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* BIT(2) - TrnPDataQP_sts parity status
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* BIT(3) - BIT(6) - TrnPDataQRF[0:3]_sts parity status
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* BIT(7) - TrnNpHdrQP_sts parity status
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* BIT(8) - BIT(9) - TrnNpHdrQRF[0:1]_sts parity status
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* BIT(10) - TrnCplHdrQ_sts parity status
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* BIT(11) - TrnPutObsReqQ_sts parity status
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* BIT(12) - TrnPushReqQ_sts parity status
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* BIT(13) - SbSplitIdRam_sts parity status
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* BIT(14) - SbReqCountQ_sts parity status
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* BIT(15) - SbCplTrkRam_sts parity status
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* BIT(16) - SbGetObsReqQ_sts parity status
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* BIT(17) - SbEpochIdQ_sts parity status
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* BIT(18) - SbAtCplHdrQ_sts parity status
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* BIT(19) - SbAtCplDataQ_sts parity status
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* BIT(20) - SbReqCountRam_sts parity status
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* BIT(21) - SbAtCplHdrQ_sc_sts parity status
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*/
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#define ADF_GEN6_TI_TRNSB_PAR_STS_MASK \
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(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | \
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BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | \
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BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | \
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BIT(19) | BIT(20) | BIT(21))
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/* Status register to log misc error on RI */
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#define ADF_GEN6_RIMISCSTS 0x41B1B8
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/* Status control register to log misc RI error */
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#define ADF_GEN6_RIMISCCTL 0x41B1BC
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/*
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* ERRSOU2 bit mask
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* BIT(0) - SSM Interrupt Mask
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* BIT(1) - CFC on CPP. ORed of CFC Push error and Pull error
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* BIT(2) - BIT(4) - CPP attention interrupts
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* BIT(18) - PM interrupt
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*/
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#define ADF_GEN6_ERRSOU2_SSM_ERR_BIT BIT(0)
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#define ADF_GEN6_ERRSOU2_CPP_CFC_ERR_STATUS_BIT BIT(1)
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#define ADF_GEN6_ERRSOU2_CPP_CFC_ATT_INT_MASK \
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(BIT(2) | BIT(3) | BIT(4))
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#define ADF_GEN6_ERRSOU2_PM_INT_BIT BIT(18)
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#define ADF_GEN6_ERRSOU2_MASK \
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(ADF_GEN6_ERRSOU2_SSM_ERR_BIT | \
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ADF_GEN6_ERRSOU2_CPP_CFC_ERR_STATUS_BIT)
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#define ADF_GEN6_ERRSOU2_DIS_MASK \
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(ADF_GEN6_ERRSOU2_SSM_ERR_BIT | \
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ADF_GEN6_ERRSOU2_CPP_CFC_ERR_STATUS_BIT | \
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ADF_GEN6_ERRSOU2_CPP_CFC_ATT_INT_MASK)
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#define ADF_GEN6_IAINTSTATSSM 0x28
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/* IAINTSTATSSM error bit mask definitions */
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#define ADF_GEN6_IAINTSTATSSM_SH_ERR_BIT BIT(0)
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#define ADF_GEN6_IAINTSTATSSM_PPERR_BIT BIT(2)
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#define ADF_GEN6_IAINTSTATSSM_SCMPAR_ERR_BIT BIT(4)
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#define ADF_GEN6_IAINTSTATSSM_CPPPAR_ERR_BIT BIT(5)
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#define ADF_GEN6_IAINTSTATSSM_RFPAR_ERR_BIT BIT(6)
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#define ADF_GEN6_IAINTSTATSSM_UNEXP_CPL_ERR_BIT BIT(7)
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#define ADF_GEN6_IAINTSTATSSM_MASK \
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(ADF_GEN6_IAINTSTATSSM_SH_ERR_BIT | \
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ADF_GEN6_IAINTSTATSSM_PPERR_BIT | \
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ADF_GEN6_IAINTSTATSSM_SCMPAR_ERR_BIT | \
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ADF_GEN6_IAINTSTATSSM_CPPPAR_ERR_BIT | \
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ADF_GEN6_IAINTSTATSSM_RFPAR_ERR_BIT | \
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ADF_GEN6_IAINTSTATSSM_UNEXP_CPL_ERR_BIT)
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#define ADF_GEN6_UERRSSMSH 0x18
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/*
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* UERRSSMSH error bit mask definitions
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*
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* BIT(0) - Indicates one uncorrectable error
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* BIT(15) - Indicates multiple uncorrectable errors
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* in device shared memory
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*/
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#define ADF_GEN6_UERRSSMSH_MASK (BIT(0) | BIT(15))
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/*
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* CERRSSMSH error bit
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* BIT(0) - Indicates one correctable error
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*/
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#define ADF_GEN6_CERRSSMSH_ERROR_BIT (BIT(0) | BIT(15) | BIT(24))
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#define ADF_GEN6_CERRSSMSH 0x10
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#define ADF_GEN6_INTMASKSSM 0x0
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/*
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* Error reporting mask in INTMASKSSM
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* BIT(0) - Shared memory uncorrectable interrupt mask
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* BIT(2) - PPERR interrupt mask
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* BIT(4) - SCM parity error interrupt mask
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* BIT(5) - CPP parity error interrupt mask
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* BIT(6) - SHRAM RF parity error interrupt mask
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* BIT(7) - AXI unexpected completion error mask
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*/
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#define ADF_GEN6_INTMASKSSM_MASK \
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(BIT(0) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | BIT(7))
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/* CPP push or pull error */
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#define ADF_GEN6_PPERR 0x8
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#define ADF_GEN6_PPERR_MASK (BIT(0) | BIT(1))
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/*
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* SSM_FERR_STATUS error bit mask definitions
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*/
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#define ADF_GEN6_SCM_PAR_ERR_MASK BIT(5)
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#define ADF_GEN6_CPP_PAR_ERR_MASK (BIT(0) | BIT(1) | BIT(2))
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#define ADF_GEN6_UNEXP_CPL_ERR_MASK (BIT(3) | BIT(4) | BIT(10) | BIT(11))
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#define ADF_GEN6_RF_PAR_ERR_MASK BIT(16)
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#define ADF_GEN6_SSM_FERR_STATUS 0x9C
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#define ADF_GEN6_CPP_CFC_ERR_STATUS 0x640C04
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/*
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* BIT(0) - Indicates one or more CPP CFC errors
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* BIT(1) - Indicates multiple CPP CFC errors
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* BIT(7) - Indicates CPP CFC command parity error type
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* BIT(8) - Indicates CPP CFC data parity error type
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*/
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#define ADF_GEN6_CPP_CFC_ERR_STATUS_ERR_BIT BIT(0)
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#define ADF_GEN6_CPP_CFC_ERR_STATUS_MERR_BIT BIT(1)
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#define ADF_GEN6_CPP_CFC_ERR_STATUS_CMDPAR_BIT BIT(7)
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#define ADF_GEN6_CPP_CFC_ERR_STATUS_DATAPAR_BIT BIT(8)
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#define ADF_GEN6_CPP_CFC_FATAL_ERR_BIT \
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(ADF_GEN6_CPP_CFC_ERR_STATUS_ERR_BIT | \
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ADF_GEN6_CPP_CFC_ERR_STATUS_MERR_BIT)
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/*
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* BIT(0) - Enables CFC to detect and log a push/pull data error
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* BIT(1) - Enables CFC to generate interrupt to PCIEP for a CPP error
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* BIT(4) - When 1 parity detection is disabled
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* BIT(5) - When 1 parity detection is disabled on CPP command bus
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* BIT(6) - When 1 parity detection is disabled on CPP push/pull bus
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* BIT(9) - When 1 RF parity error detection is disabled
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*/
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#define ADF_GEN6_CPP_CFC_ERR_CTRL_MASK (BIT(0) | BIT(1))
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#define ADF_GEN6_CPP_CFC_ERR_CTRL_DIS_MASK \
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(BIT(4) | BIT(5) | BIT(6) | BIT(9) | BIT(10))
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#define ADF_GEN6_CPP_CFC_ERR_CTRL 0x640C00
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/*
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* BIT(0) - Clears bit(0) of ADF_GEN6_CPP_CFC_ERR_STATUS
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* when an error is reported on CPP
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* BIT(1) - Clears bit(1) of ADF_GEN6_CPP_CFC_ERR_STATUS
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* when multiple errors are reported on CPP
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* BIT(2) - Clears bit(2) of ADF_GEN6_CPP_CFC_ERR_STATUS
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* when attention interrupt is reported
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*/
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#define ADF_GEN6_CPP_CFC_ERR_STATUS_CLR_MASK (BIT(0) | BIT(1) | BIT(2))
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#define ADF_GEN6_CPP_CFC_ERR_STATUS_CLR 0x640C08
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/*
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* ERRSOU3 bit masks
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* BIT(0) - indicates error response order overflow and/or BME error
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* BIT(1) - indicates RI push/pull error
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* BIT(2) - indicates TI push/pull error
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* BIT(5) - indicates TI pull parity error
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* BIT(6) - indicates RI push parity error
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* BIT(7) - indicates VFLR interrupt
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* BIT(8) - indicates ring pair interrupts for ATU detected fault
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* BIT(9) - indicates rate limiting error
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*/
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#define ADF_GEN6_ERRSOU3_TIMISCSTS_BIT BIT(0)
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#define ADF_GEN6_ERRSOU3_RICPPINTSTS_MASK (BIT(1) | BIT(6))
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#define ADF_GEN6_ERRSOU3_TICPPINTSTS_MASK (BIT(2) | BIT(5))
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#define ADF_GEN6_ERRSOU3_VFLRNOTIFY_BIT BIT(7)
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#define ADF_GEN6_ERRSOU3_ATUFAULTSTATUS_BIT BIT(8)
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#define ADF_GEN6_ERRSOU3_RLTERROR_BIT BIT(9)
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#define ADF_GEN6_ERRSOU3_TC_VC_MAP_ERROR_BIT BIT(16)
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#define ADF_GEN6_ERRSOU3_PCIE_DEVHALT_BIT BIT(17)
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#define ADF_GEN6_ERRSOU3_PG_REQ_DEVHALT_BIT BIT(18)
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#define ADF_GEN6_ERRSOU3_XLT_CPL_DEVHALT_BIT BIT(19)
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#define ADF_GEN6_ERRSOU3_TI_INT_ERR_DEVHALT_BIT BIT(20)
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#define ADF_GEN6_ERRSOU3_MASK ( \
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(ADF_GEN6_ERRSOU3_TIMISCSTS_BIT) | \
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(ADF_GEN6_ERRSOU3_RICPPINTSTS_MASK) | \
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(ADF_GEN6_ERRSOU3_TICPPINTSTS_MASK) | \
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(ADF_GEN6_ERRSOU3_VFLRNOTIFY_BIT) | \
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(ADF_GEN6_ERRSOU3_ATUFAULTSTATUS_BIT) | \
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(ADF_GEN6_ERRSOU3_RLTERROR_BIT) | \
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(ADF_GEN6_ERRSOU3_TC_VC_MAP_ERROR_BIT) | \
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(ADF_GEN6_ERRSOU3_PCIE_DEVHALT_BIT) | \
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(ADF_GEN6_ERRSOU3_PG_REQ_DEVHALT_BIT) | \
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(ADF_GEN6_ERRSOU3_XLT_CPL_DEVHALT_BIT) | \
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(ADF_GEN6_ERRSOU3_TI_INT_ERR_DEVHALT_BIT))
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#define ADF_GEN6_ERRSOU3_DIS_MASK ( \
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(ADF_GEN6_ERRSOU3_TIMISCSTS_BIT) | \
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(ADF_GEN6_ERRSOU3_RICPPINTSTS_MASK) | \
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(ADF_GEN6_ERRSOU3_TICPPINTSTS_MASK) | \
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(ADF_GEN6_ERRSOU3_VFLRNOTIFY_BIT) | \
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(ADF_GEN6_ERRSOU3_ATUFAULTSTATUS_BIT) | \
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(ADF_GEN6_ERRSOU3_RLTERROR_BIT) | \
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(ADF_GEN6_ERRSOU3_TC_VC_MAP_ERROR_BIT))
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/* Rate limiting error log register */
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#define ADF_GEN6_RLT_ERRLOG 0x508814
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#define ADF_GEN6_RLT_ERRLOG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
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/* TI misc status register */
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#define ADF_GEN6_TIMISCSTS 0x50054C
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/* TI misc error reporting mask */
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#define ADF_GEN6_TIMISCCTL 0x500548
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/*
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* TI Misc error reporting control mask
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* BIT(0) - Enables error detection and logging in TIMISCSTS register
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* BIT(1) - It has effect only when SRIOV enabled, this bit is 0 by default
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* BIT(2) - Enables the D-F-x counter within the dispatch arbiter
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* to start based on the command triggered from
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* BIT(30) - Disables VFLR functionality
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* bits 1, 2 and 30 value should be preserved and not meant to be changed
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* within RAS.
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*/
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#define ADF_GEN6_TIMISCCTL_BIT BIT(0)
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#define ADF_GEN6_TIMSCCTL_RELAY_MASK (BIT(1) | BIT(2) | BIT(30))
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/* RI CPP interface status register */
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#define ADF_GEN6_RICPPINTSTS 0x41A330
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/*
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* Uncorrectable error mask in RICPPINTSTS register
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* BIT(0) - RI asserted the CPP error signal during a push
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* BIT(1) - RI detected the CPP error signal asserted during a pull
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* BIT(2) - RI detected a push data parity error
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* BIT(3) - RI detected a push valid parity error
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*/
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#define ADF_GEN6_RICPPINTSTS_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
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/* RI CPP interface register control */
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#define ADF_GEN6_RICPPINTCTL 0x41A32C
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/*
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* Control bit mask for RICPPINTCTL register
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* BIT(0) - value of 1 enables error detection and reporting
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* on the RI CPP Push interface
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* BIT(1) - value of 1 enables error detection and reporting
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* on the RI CPP Pull interface
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* BIT(2) - value of 1 enables error detection and reporting
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* on the RI Parity
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* BIT(3) - value of 1 enable checking parity on CPP
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*/
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#define ADF_GEN6_RICPPINTCTL_MASK \
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(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))
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/* TI CPP interface status register */
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#define ADF_GEN6_TICPPINTSTS 0x50053C
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/*
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* Uncorrectable error mask in TICPPINTSTS register
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* BIT(0) - value of 1 indicates that the TI asserted
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* the CPP error signal during a push
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* BIT(1) - value of 1 indicates that the TI detected
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* the CPP error signal asserted during a pull
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* BIT(2) - value of 1 indicates that the TI detected
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* a pull data parity error
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*/
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#define ADF_GEN6_TICPPINTSTS_MASK (BIT(0) | BIT(1) | BIT(2))
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/* TI CPP interface status register control */
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#define ADF_GEN6_TICPPINTCTL 0x500538
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/*
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* Control bit mask for TICPPINTCTL register
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* BIT(0) - value of 1 enables error detection and reporting on
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* the TI CPP Push interface
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* BIT(1) - value of 1 enables error detection and reporting on
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* the TI CPP Push interface
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* BIT(2) - value of 1 enables parity error detection and logging on
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* the TI CPP Pull interface
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* BIT(3) - value of 1 enables CPP CMD and Pull Data parity checking
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*/
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#define ADF_GEN6_TICPPINTCTL_MASK \
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(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))
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/* ATU fault status register */
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#define ADF_GEN6_ATUFAULTSTATUS(i) (0x506000 + ((i) * 0x4))
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#define ADF_GEN6_ATUFAULTSTATUS_BIT BIT(0)
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/* Command parity error detected on IOSFP command to QAT */
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#define ADF_GEN6_RIMISCSTS_BIT BIT(0)
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#define ADF_GEN6_GENSTS 0x41A220
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#define ADF_GEN6_GENSTS_DEVICE_STATE_MASK GENMASK(1, 0)
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#define ADF_GEN6_GENSTS_RESET_TYPE_MASK GENMASK(3, 2)
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#define ADF_GEN6_GENSTS_PFLR 0x1
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#define ADF_GEN6_GENSTS_COLD_RESET 0x3
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#define ADF_GEN6_GENSTS_DEVHALT 0x1
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void adf_gen6_init_ras_ops(struct adf_ras_ops *ras_ops);
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#endif /* ADF_GEN6_RAS_H_ */
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