393 lines
11 KiB
C
393 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
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*/
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#include <drm/drm_managed.h>
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#include "dpu_kms.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hwio.h"
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#include "dpu_hw_lm.h"
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#include "dpu_hw_mdss.h"
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#define LM_OP_MODE 0x00
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#define LM_OUT_SIZE 0x04
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#define LM_BORDER_COLOR_0 0x08
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#define LM_BORDER_COLOR_1 0x010
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/* These register are offset to mixer base + stage base */
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#define LM_BLEND0_OP 0x00
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/* <v12 DPU with offset to mixer base + stage base */
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#define LM_BLEND0_CONST_ALPHA 0x04
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#define LM_FG_COLOR_FILL_COLOR_0 0x08
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#define LM_FG_COLOR_FILL_COLOR_1 0x0C
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#define LM_FG_COLOR_FILL_SIZE 0x10
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#define LM_FG_COLOR_FILL_XY 0x14
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/* >= v12 DPU */
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#define LM_BG_SRC_SEL_V12 0x14
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#define LM_BG_SRC_SEL_V12_RESET_VALUE 0x0000c0c0
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#define LM_BORDER_COLOR_0_V12 0x1c
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#define LM_BORDER_COLOR_1_V12 0x20
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/* >= v12 DPU with offset to mixer base + stage base */
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#define LM_BLEND0_FG_SRC_SEL_V12 0x04
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#define LM_BLEND0_CONST_ALPHA_V12 0x08
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#define LM_FG_COLOR_FILL_COLOR_0_V12 0x0c
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#define LM_FG_COLOR_FILL_COLOR_1_V12 0x10
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#define LM_FG_COLOR_FILL_SIZE_V12 0x14
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#define LM_FG_COLOR_FILL_XY_V12 0x18
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#define LM_BLEND0_FG_ALPHA 0x04
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#define LM_BLEND0_BG_ALPHA 0x08
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#define LM_MISR_CTRL 0x310
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#define LM_MISR_SIGNATURE 0x314
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/**
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* _stage_offset(): returns the relative offset of the blend registers
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* for the stage to be setup
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* @ctx: mixer ctx contains the mixer to be programmed
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* @stage: stage index to setup
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*/
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static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage)
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{
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const struct dpu_lm_sub_blks *sblk = ctx->cap->sblk;
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if (stage != DPU_STAGE_BASE && stage <= sblk->maxblendstages)
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return sblk->blendstage_base[stage - DPU_STAGE_0];
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return -EINVAL;
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}
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static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx,
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struct dpu_hw_mixer_cfg *mixer)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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u32 outsize;
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u32 op_mode;
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op_mode = DPU_REG_READ(c, LM_OP_MODE);
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outsize = mixer->out_height << 16 | mixer->out_width;
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DPU_REG_WRITE(c, LM_OUT_SIZE, outsize);
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/* SPLIT_LEFT_RIGHT */
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if (mixer->right_mixer)
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op_mode |= BIT(31);
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else
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op_mode &= ~BIT(31);
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DPU_REG_WRITE(c, LM_OP_MODE, op_mode);
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}
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static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,
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struct dpu_mdss_color *color,
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u8 border_en)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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if (border_en) {
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DPU_REG_WRITE(c, LM_BORDER_COLOR_0,
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(color->color_0 & 0xFFF) |
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((color->color_1 & 0xFFF) << 0x10));
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DPU_REG_WRITE(c, LM_BORDER_COLOR_1,
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(color->color_2 & 0xFFF) |
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((color->color_3 & 0xFFF) << 0x10));
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}
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}
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static void dpu_hw_lm_setup_border_color_v12(struct dpu_hw_mixer *ctx,
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struct dpu_mdss_color *color,
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u8 border_en)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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if (border_en) {
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DPU_REG_WRITE(c, LM_BORDER_COLOR_0_V12,
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(color->color_0 & 0x3ff) |
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((color->color_1 & 0x3ff) << 16));
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DPU_REG_WRITE(c, LM_BORDER_COLOR_1_V12,
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(color->color_2 & 0x3ff) |
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((color->color_3 & 0x3ff) << 16));
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}
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}
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static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)
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{
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dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0);
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}
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static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)
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{
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return dpu_hw_collect_misr(&ctx->hw, LM_MISR_CTRL, LM_MISR_SIGNATURE, misr_value);
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}
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static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx,
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u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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int stage_off;
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u32 const_alpha;
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if (stage == DPU_STAGE_BASE)
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return;
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stage_off = _stage_offset(ctx, stage);
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if (WARN_ON(stage_off < 0))
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return;
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const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16);
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DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha);
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DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
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}
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static void
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dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx,
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u32 stage, u32 fg_alpha,
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u32 bg_alpha, u32 blend_op)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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int stage_off;
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u32 const_alpha;
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if (stage == DPU_STAGE_BASE)
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return;
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stage_off = _stage_offset(ctx, stage);
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if (WARN_ON(stage_off < 0))
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return;
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const_alpha = (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16);
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DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha);
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DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
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}
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static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx,
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u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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int stage_off;
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if (stage == DPU_STAGE_BASE)
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return;
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stage_off = _stage_offset(ctx, stage);
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if (WARN_ON(stage_off < 0))
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return;
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DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha);
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DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha);
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DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
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}
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static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx,
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uint32_t mixer_op_mode)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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int op_mode;
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/* read the existing op_mode configuration */
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op_mode = DPU_REG_READ(c, LM_OP_MODE);
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op_mode = (op_mode & (BIT(31) | BIT(30))) | mixer_op_mode;
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DPU_REG_WRITE(c, LM_OP_MODE, op_mode);
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}
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static void dpu_hw_lm_setup_color3_v12(struct dpu_hw_mixer *ctx,
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uint32_t mixer_op_mode)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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int op_mode, stages, stage_off, i;
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stages = ctx->cap->sblk->maxblendstages;
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if (stages <= 0)
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return;
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for (i = DPU_STAGE_0; i <= stages; i++) {
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stage_off = _stage_offset(ctx, i);
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if (WARN_ON(stage_off < 0))
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return;
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/* set color_out3 bit in blend0_op when enabled in mixer_op_mode */
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op_mode = DPU_REG_READ(c, LM_BLEND0_OP + stage_off);
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if (mixer_op_mode & BIT(i))
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op_mode |= BIT(30);
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else
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op_mode &= ~BIT(30);
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DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, op_mode);
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}
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}
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static int _set_staged_sspp(u32 stage, struct dpu_hw_stage_cfg *stage_cfg,
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int pipes_per_stage, u32 *value)
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{
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int i;
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u32 pipe_type = 0, pipe_id = 0, rec_id = 0;
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u32 src_sel[PIPES_PER_STAGE];
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*value = LM_BG_SRC_SEL_V12_RESET_VALUE;
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if (!stage_cfg || !pipes_per_stage)
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return 0;
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for (i = 0; i < pipes_per_stage; i++) {
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enum dpu_sspp pipe = stage_cfg->stage[stage][i];
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enum dpu_sspp_multirect_index rect_index = stage_cfg->multirect_index[stage][i];
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src_sel[i] = LM_BG_SRC_SEL_V12_RESET_VALUE;
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if (!pipe)
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continue;
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/* translate pipe data to SWI pipe_type, pipe_id */
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if (pipe >= SSPP_DMA0 && pipe <= SSPP_DMA5) {
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pipe_type = 0;
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pipe_id = pipe - SSPP_DMA0;
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} else if (pipe >= SSPP_VIG0 && pipe <= SSPP_VIG3) {
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pipe_type = 1;
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pipe_id = pipe - SSPP_VIG0;
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} else {
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DPU_ERROR("invalid rec-%d pipe:%d\n", i, pipe);
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return -EINVAL;
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}
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/* translate rec data to SWI rec_id */
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if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) {
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rec_id = 0;
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} else if (rect_index == DPU_SSPP_RECT_1) {
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rec_id = 1;
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} else {
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DPU_ERROR("invalid rec-%d rect_index:%d\n", i, rect_index);
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rec_id = 0;
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}
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/* calculate SWI value for rec-0 and rec-1 and store it temporary buffer */
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src_sel[i] = (((pipe_type & 0x3) << 6) | ((rec_id & 0x3) << 4) | (pipe_id & 0xf));
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}
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/* calculate final SWI register value for rec-0 and rec-1 */
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*value = 0;
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for (i = 0; i < pipes_per_stage; i++)
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*value |= src_sel[i] << (i * 8);
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return 0;
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}
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static int dpu_hw_lm_setup_blendstage(struct dpu_hw_mixer *ctx, enum dpu_lm lm,
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struct dpu_hw_stage_cfg *stage_cfg)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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int i, ret, stages, stage_off, pipes_per_stage;
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u32 value;
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stages = ctx->cap->sblk->maxblendstages;
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if (stages <= 0)
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return -EINVAL;
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if (test_bit(DPU_MIXER_SOURCESPLIT, &ctx->cap->features))
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pipes_per_stage = PIPES_PER_STAGE;
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else
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pipes_per_stage = 1;
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/*
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* When stage configuration is empty, we can enable the
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* border color by setting the corresponding LAYER_ACTIVE bit
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* and un-staging all the pipes from the layer mixer.
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*/
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if (!stage_cfg)
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DPU_REG_WRITE(c, LM_BG_SRC_SEL_V12, LM_BG_SRC_SEL_V12_RESET_VALUE);
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for (i = DPU_STAGE_0; i <= stages; i++) {
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stage_off = _stage_offset(ctx, i);
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if (stage_off < 0)
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return stage_off;
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ret = _set_staged_sspp(i, stage_cfg, pipes_per_stage, &value);
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if (ret)
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return ret;
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DPU_REG_WRITE(c, LM_BLEND0_FG_SRC_SEL_V12 + stage_off, value);
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}
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return 0;
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}
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static int dpu_hw_lm_clear_all_blendstages(struct dpu_hw_mixer *ctx)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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int i, stages, stage_off;
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stages = ctx->cap->sblk->maxblendstages;
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if (stages <= 0)
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return -EINVAL;
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DPU_REG_WRITE(c, LM_BG_SRC_SEL_V12, LM_BG_SRC_SEL_V12_RESET_VALUE);
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for (i = DPU_STAGE_0; i <= stages; i++) {
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stage_off = _stage_offset(ctx, i);
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if (stage_off < 0)
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return stage_off;
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DPU_REG_WRITE(c, LM_BLEND0_FG_SRC_SEL_V12 + stage_off,
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LM_BG_SRC_SEL_V12_RESET_VALUE);
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}
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return 0;
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}
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/**
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* dpu_hw_lm_init() - Initializes the mixer hw driver object.
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* should be called once before accessing every mixer.
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* @dev: Corresponding device for devres management
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* @cfg: mixer catalog entry for which driver object is required
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* @addr: mapped register io address of MDP
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* @mdss_ver: DPU core's major and minor versions
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*/
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struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,
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const struct dpu_lm_cfg *cfg,
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void __iomem *addr,
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const struct dpu_mdss_version *mdss_ver)
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{
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struct dpu_hw_mixer *c;
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if (cfg->pingpong == PINGPONG_NONE) {
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DPU_DEBUG("skip mixer %d without pingpong\n", cfg->id);
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return NULL;
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}
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c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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c->hw.blk_addr = addr + cfg->base;
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c->hw.log_mask = DPU_DBG_MASK_LM;
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/* Assign ops */
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c->idx = cfg->id;
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c->cap = cfg;
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c->ops.setup_mixer_out = dpu_hw_lm_setup_out;
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if (mdss_ver->core_major_ver >= 12)
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c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha_v12;
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else if (mdss_ver->core_major_ver >= 4)
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c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;
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else
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c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config;
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if (mdss_ver->core_major_ver < 12) {
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c->ops.setup_alpha_out = dpu_hw_lm_setup_color3;
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c->ops.setup_border_color = dpu_hw_lm_setup_border_color;
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} else {
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c->ops.setup_alpha_out = dpu_hw_lm_setup_color3_v12;
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c->ops.setup_blendstage = dpu_hw_lm_setup_blendstage;
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c->ops.clear_all_blendstages = dpu_hw_lm_clear_all_blendstages;
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c->ops.setup_border_color = dpu_hw_lm_setup_border_color_v12;
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}
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c->ops.setup_misr = dpu_hw_lm_setup_misr;
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c->ops.collect_misr = dpu_hw_lm_collect_misr;
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return c;
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}
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