540 lines
14 KiB
C
540 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/bits.h>
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#include <linux/i2c.h>
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#include <linux/i2c-mux.h>
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#include <linux/mod_devicetable.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/unaligned.h>
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enum rtl9300_bus_freq {
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RTL9300_I2C_STD_FREQ,
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RTL9300_I2C_FAST_FREQ,
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};
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struct rtl9300_i2c;
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struct rtl9300_i2c_chan {
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struct i2c_adapter adap;
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struct rtl9300_i2c *i2c;
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enum rtl9300_bus_freq bus_freq;
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u8 sda_num;
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};
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enum rtl9300_i2c_reg_scope {
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REG_SCOPE_GLOBAL,
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REG_SCOPE_MASTER,
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};
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struct rtl9300_i2c_reg_field {
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struct reg_field field;
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enum rtl9300_i2c_reg_scope scope;
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};
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enum rtl9300_i2c_reg_fields {
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F_DATA_WIDTH = 0,
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F_DEV_ADDR,
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F_I2C_FAIL,
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F_I2C_TRIG,
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F_MEM_ADDR,
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F_MEM_ADDR_WIDTH,
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F_RD_MODE,
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F_RWOP,
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F_SCL_FREQ,
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F_SCL_SEL,
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F_SDA_OUT_SEL,
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F_SDA_SEL,
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/* keep last */
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F_NUM_FIELDS
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};
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struct rtl9300_i2c_drv_data {
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struct rtl9300_i2c_reg_field field_desc[F_NUM_FIELDS];
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int (*select_scl)(struct rtl9300_i2c *i2c, u8 scl);
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u32 data_reg;
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u8 max_nchan;
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};
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#define RTL9300_I2C_MUX_NCHAN 8
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#define RTL9310_I2C_MUX_NCHAN 12
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struct rtl9300_i2c {
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struct regmap *regmap;
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struct device *dev;
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struct rtl9300_i2c_chan chans[RTL9310_I2C_MUX_NCHAN];
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struct regmap_field *fields[F_NUM_FIELDS];
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u32 reg_base;
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u32 data_reg;
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u8 scl_num;
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u8 sda_num;
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struct mutex lock;
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};
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DEFINE_GUARD(rtl9300_i2c, struct rtl9300_i2c *, mutex_lock(&_T->lock), mutex_unlock(&_T->lock))
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enum rtl9300_i2c_xfer_type {
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RTL9300_I2C_XFER_BYTE,
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RTL9300_I2C_XFER_WORD,
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RTL9300_I2C_XFER_BLOCK,
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};
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struct rtl9300_i2c_xfer {
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enum rtl9300_i2c_xfer_type type;
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u16 dev_addr;
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u8 reg_addr;
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u8 reg_addr_len;
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u8 *data;
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u8 data_len;
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bool write;
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};
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#define RTL9300_I2C_MST_CTRL1 0x0
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#define RTL9300_I2C_MST_CTRL2 0x4
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#define RTL9300_I2C_MST_DATA_WORD0 0x8
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#define RTL9300_I2C_MST_DATA_WORD1 0xc
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#define RTL9300_I2C_MST_DATA_WORD2 0x10
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#define RTL9300_I2C_MST_DATA_WORD3 0x14
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#define RTL9300_I2C_MST_GLB_CTRL 0x384
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#define RTL9310_I2C_MST_IF_CTRL 0x1004
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#define RTL9310_I2C_MST_IF_SEL 0x1008
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#define RTL9310_I2C_MST_CTRL 0x0
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#define RTL9310_I2C_MST_MEMADDR_CTRL 0x4
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#define RTL9310_I2C_MST_DATA_CTRL 0x8
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static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len)
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{
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int ret;
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ret = regmap_field_write(i2c->fields[F_MEM_ADDR_WIDTH], len);
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if (ret)
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return ret;
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return regmap_field_write(i2c->fields[F_MEM_ADDR], reg);
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}
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static int rtl9300_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl)
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{
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return regmap_field_write(i2c->fields[F_SCL_SEL], 1);
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}
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static int rtl9310_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl)
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{
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return regmap_field_update_bits(i2c->fields[F_SCL_SEL], BIT(scl), BIT(scl));
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}
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static int rtl9300_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan)
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{
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struct rtl9300_i2c_drv_data *drv_data;
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int ret;
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if (i2c->sda_num == chan->sda_num)
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return 0;
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ret = regmap_field_write(i2c->fields[F_SCL_FREQ], chan->bus_freq);
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if (ret)
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return ret;
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drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev);
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ret = drv_data->select_scl(i2c, i2c->scl_num);
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if (ret)
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return ret;
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ret = regmap_field_update_bits(i2c->fields[F_SDA_SEL], BIT(chan->sda_num),
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BIT(chan->sda_num));
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if (ret)
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return ret;
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ret = regmap_field_write(i2c->fields[F_SDA_OUT_SEL], chan->sda_num);
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if (ret)
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return ret;
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i2c->sda_num = chan->sda_num;
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return 0;
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}
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static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, u8 len)
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{
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u32 vals[4] = {};
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int i, ret;
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if (len > 16)
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return -EIO;
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ret = regmap_bulk_read(i2c->regmap, i2c->data_reg, vals, ARRAY_SIZE(vals));
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if (ret)
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return ret;
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for (i = 0; i < len; i++) {
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buf[i] = vals[i/4] & 0xff;
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vals[i/4] >>= 8;
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}
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return 0;
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}
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static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, u8 len)
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{
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u32 vals[4] = {};
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int i;
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if (len > 16)
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return -EIO;
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for (i = 0; i < len; i++) {
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unsigned int shift = (i % 4) * 8;
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unsigned int reg = i / 4;
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vals[reg] |= buf[i] << shift;
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}
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return regmap_bulk_write(i2c->regmap, i2c->data_reg, vals, ARRAY_SIZE(vals));
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}
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static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data)
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{
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return regmap_write(i2c->regmap, i2c->data_reg, data);
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}
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static int rtl9300_i2c_prepare_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_xfer *xfer)
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{
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int ret;
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if (xfer->data_len < 1 || xfer->data_len > 16)
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return -EINVAL;
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ret = regmap_field_write(i2c->fields[F_DEV_ADDR], xfer->dev_addr);
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if (ret)
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return ret;
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ret = rtl9300_i2c_reg_addr_set(i2c, xfer->reg_addr, xfer->reg_addr_len);
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if (ret)
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return ret;
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ret = regmap_field_write(i2c->fields[F_RWOP], xfer->write);
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if (ret)
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return ret;
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ret = regmap_field_write(i2c->fields[F_DATA_WIDTH], (xfer->data_len - 1) & 0xf);
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if (ret)
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return ret;
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if (xfer->write) {
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switch (xfer->type) {
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case RTL9300_I2C_XFER_BYTE:
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ret = rtl9300_i2c_writel(i2c, *xfer->data);
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break;
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case RTL9300_I2C_XFER_WORD:
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ret = rtl9300_i2c_writel(i2c, get_unaligned((const u16 *)xfer->data));
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break;
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default:
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ret = rtl9300_i2c_write(i2c, xfer->data, xfer->data_len);
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break;
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}
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}
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return ret;
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}
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static int rtl9300_i2c_do_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_xfer *xfer)
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{
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u32 val;
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int ret;
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ret = regmap_field_write(i2c->fields[F_I2C_TRIG], 1);
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if (ret)
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return ret;
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ret = regmap_field_read_poll_timeout(i2c->fields[F_I2C_TRIG], val, !val, 100, 100000);
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if (ret)
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return ret;
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ret = regmap_field_read(i2c->fields[F_I2C_FAIL], &val);
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if (ret)
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return ret;
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if (val)
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return -EIO;
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if (!xfer->write) {
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switch (xfer->type) {
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case RTL9300_I2C_XFER_BYTE:
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ret = regmap_read(i2c->regmap, i2c->data_reg, &val);
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if (ret)
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return ret;
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*xfer->data = val & 0xff;
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break;
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case RTL9300_I2C_XFER_WORD:
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ret = regmap_read(i2c->regmap, i2c->data_reg, &val);
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if (ret)
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return ret;
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put_unaligned(val & 0xffff, (u16*)xfer->data);
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break;
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default:
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ret = rtl9300_i2c_read(i2c, xfer->data, xfer->data_len);
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if (ret)
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return ret;
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break;
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}
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}
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return 0;
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}
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static int rtl9300_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, unsigned short flags,
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char read_write, u8 command, int size,
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union i2c_smbus_data *data)
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{
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struct rtl9300_i2c_chan *chan = i2c_get_adapdata(adap);
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struct rtl9300_i2c *i2c = chan->i2c;
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struct rtl9300_i2c_xfer xfer = {0};
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int ret;
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if (addr > 0x7f)
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return -EINVAL;
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guard(rtl9300_i2c)(i2c);
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ret = rtl9300_i2c_config_chan(i2c, chan);
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if (ret)
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return ret;
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xfer.dev_addr = addr & 0x7f;
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xfer.write = (read_write == I2C_SMBUS_WRITE);
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xfer.reg_addr = command;
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xfer.reg_addr_len = 1;
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switch (size) {
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case I2C_SMBUS_BYTE:
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xfer.data = (read_write == I2C_SMBUS_READ) ? &data->byte : &command;
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xfer.data_len = 1;
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xfer.reg_addr = 0;
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xfer.reg_addr_len = 0;
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xfer.type = RTL9300_I2C_XFER_BYTE;
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break;
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case I2C_SMBUS_BYTE_DATA:
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xfer.data = &data->byte;
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xfer.data_len = 1;
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xfer.type = RTL9300_I2C_XFER_BYTE;
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break;
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case I2C_SMBUS_WORD_DATA:
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xfer.data = (u8 *)&data->word;
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xfer.data_len = 2;
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xfer.type = RTL9300_I2C_XFER_WORD;
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break;
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case I2C_SMBUS_BLOCK_DATA:
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xfer.data = &data->block[0];
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xfer.data_len = data->block[0] + 1;
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xfer.type = RTL9300_I2C_XFER_BLOCK;
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break;
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case I2C_SMBUS_I2C_BLOCK_DATA:
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xfer.data = &data->block[1];
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xfer.data_len = data->block[0];
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xfer.type = RTL9300_I2C_XFER_BLOCK;
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break;
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default:
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dev_err(&adap->dev, "Unsupported transaction %d\n", size);
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return -EOPNOTSUPP;
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}
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ret = rtl9300_i2c_prepare_xfer(i2c, &xfer);
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if (ret)
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return ret;
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return rtl9300_i2c_do_xfer(i2c, &xfer);
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}
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static u32 rtl9300_i2c_func(struct i2c_adapter *a)
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{
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return I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA |
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I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
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I2C_FUNC_SMBUS_I2C_BLOCK;
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}
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static const struct i2c_algorithm rtl9300_i2c_algo = {
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.smbus_xfer = rtl9300_i2c_smbus_xfer,
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.functionality = rtl9300_i2c_func,
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};
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static struct i2c_adapter_quirks rtl9300_i2c_quirks = {
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.flags = I2C_AQ_NO_CLK_STRETCH | I2C_AQ_NO_ZERO_LEN,
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.max_read_len = 16,
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.max_write_len = 16,
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};
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static int rtl9300_i2c_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rtl9300_i2c *i2c;
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struct fwnode_handle *child;
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struct rtl9300_i2c_drv_data *drv_data;
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struct reg_field fields[F_NUM_FIELDS];
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u32 clock_freq, scl_num, sda_num;
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int ret, i = 0;
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i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
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if (!i2c)
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return -ENOMEM;
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i2c->regmap = syscon_node_to_regmap(dev->parent->of_node);
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if (IS_ERR(i2c->regmap))
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return PTR_ERR(i2c->regmap);
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i2c->dev = dev;
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mutex_init(&i2c->lock);
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ret = device_property_read_u32(dev, "reg", &i2c->reg_base);
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if (ret)
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return ret;
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ret = device_property_read_u32(dev, "realtek,scl", &scl_num);
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if (ret || scl_num != 1)
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scl_num = 0;
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i2c->scl_num = (u8)scl_num;
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platform_set_drvdata(pdev, i2c);
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drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev);
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if (device_get_child_node_count(dev) > drv_data->max_nchan)
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return dev_err_probe(dev, -EINVAL, "Too many channels\n");
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i2c->data_reg = i2c->reg_base + drv_data->data_reg;
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for (i = 0; i < F_NUM_FIELDS; i++) {
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fields[i] = drv_data->field_desc[i].field;
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if (drv_data->field_desc[i].scope == REG_SCOPE_MASTER)
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fields[i].reg += i2c->reg_base;
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}
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ret = devm_regmap_field_bulk_alloc(dev, i2c->regmap, i2c->fields,
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fields, F_NUM_FIELDS);
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if (ret)
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return ret;
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i = 0;
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device_for_each_child_node(dev, child) {
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struct rtl9300_i2c_chan *chan = &i2c->chans[i];
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struct i2c_adapter *adap = &chan->adap;
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ret = fwnode_property_read_u32(child, "reg", &sda_num);
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if (ret)
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return ret;
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ret = fwnode_property_read_u32(child, "clock-frequency", &clock_freq);
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if (ret)
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clock_freq = I2C_MAX_STANDARD_MODE_FREQ;
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switch (clock_freq) {
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case I2C_MAX_STANDARD_MODE_FREQ:
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chan->bus_freq = RTL9300_I2C_STD_FREQ;
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break;
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case I2C_MAX_FAST_MODE_FREQ:
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chan->bus_freq = RTL9300_I2C_FAST_FREQ;
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break;
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default:
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dev_warn(i2c->dev, "SDA%d clock-frequency %d not supported using default\n",
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sda_num, clock_freq);
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break;
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}
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chan->sda_num = sda_num;
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chan->i2c = i2c;
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adap = &i2c->chans[i].adap;
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adap->owner = THIS_MODULE;
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adap->algo = &rtl9300_i2c_algo;
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adap->quirks = &rtl9300_i2c_quirks;
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adap->retries = 3;
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adap->dev.parent = dev;
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i2c_set_adapdata(adap, chan);
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adap->dev.of_node = to_of_node(child);
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snprintf(adap->name, sizeof(adap->name), "%s SDA%d\n", dev_name(dev), sda_num);
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i++;
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ret = devm_i2c_add_adapter(dev, adap);
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if (ret)
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return ret;
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}
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i2c->sda_num = 0xff;
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/* only use standard read format */
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ret = regmap_field_write(i2c->fields[F_RD_MODE], 0);
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if (ret)
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return ret;
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return 0;
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}
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#define GLB_REG_FIELD(reg, msb, lsb) \
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{ .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_GLOBAL }
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#define MST_REG_FIELD(reg, msb, lsb) \
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{ .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_MASTER }
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static const struct rtl9300_i2c_drv_data rtl9300_i2c_drv_data = {
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.field_desc = {
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[F_MEM_ADDR] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 8, 31),
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[F_SDA_OUT_SEL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 4, 6),
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[F_SCL_SEL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 3, 3),
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[F_RWOP] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 2, 2),
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[F_I2C_FAIL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 1, 1),
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[F_I2C_TRIG] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 0, 0),
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[F_RD_MODE] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 15, 15),
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[F_DEV_ADDR] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 8, 14),
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[F_DATA_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 4, 7),
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[F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 2, 3),
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[F_SCL_FREQ] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 0, 1),
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[F_SDA_SEL] = GLB_REG_FIELD(RTL9300_I2C_MST_GLB_CTRL, 0, 7),
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},
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.select_scl = rtl9300_i2c_select_scl,
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.data_reg = RTL9300_I2C_MST_DATA_WORD0,
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.max_nchan = RTL9300_I2C_MUX_NCHAN,
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};
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static const struct rtl9300_i2c_drv_data rtl9310_i2c_drv_data = {
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.field_desc = {
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[F_SCL_SEL] = GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 12, 13),
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[F_SDA_SEL] = GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 0, 11),
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[F_SCL_FREQ] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 30, 31),
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[F_DEV_ADDR] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 11, 17),
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[F_SDA_OUT_SEL] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 18, 21),
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[F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 9, 10),
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[F_DATA_WIDTH] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 5, 8),
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[F_RD_MODE] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 4, 4),
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[F_RWOP] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 2, 2),
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[F_I2C_FAIL] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 1, 1),
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[F_I2C_TRIG] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 0, 0),
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[F_MEM_ADDR] = MST_REG_FIELD(RTL9310_I2C_MST_MEMADDR_CTRL, 0, 23),
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},
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.select_scl = rtl9310_i2c_select_scl,
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.data_reg = RTL9310_I2C_MST_DATA_CTRL,
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.max_nchan = RTL9310_I2C_MUX_NCHAN,
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};
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static const struct of_device_id i2c_rtl9300_dt_ids[] = {
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{ .compatible = "realtek,rtl9301-i2c", .data = (void *) &rtl9300_i2c_drv_data },
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{ .compatible = "realtek,rtl9302b-i2c", .data = (void *) &rtl9300_i2c_drv_data },
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{ .compatible = "realtek,rtl9302c-i2c", .data = (void *) &rtl9300_i2c_drv_data },
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{ .compatible = "realtek,rtl9303-i2c", .data = (void *) &rtl9300_i2c_drv_data },
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{ .compatible = "realtek,rtl9310-i2c", .data = (void *) &rtl9310_i2c_drv_data },
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{ .compatible = "realtek,rtl9311-i2c", .data = (void *) &rtl9310_i2c_drv_data },
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{ .compatible = "realtek,rtl9312-i2c", .data = (void *) &rtl9310_i2c_drv_data },
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{ .compatible = "realtek,rtl9313-i2c", .data = (void *) &rtl9310_i2c_drv_data },
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{}
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};
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MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids);
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static struct platform_driver rtl9300_i2c_driver = {
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.probe = rtl9300_i2c_probe,
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.driver = {
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.name = "i2c-rtl9300",
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.of_match_table = i2c_rtl9300_dt_ids,
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},
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};
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module_platform_driver(rtl9300_i2c_driver);
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MODULE_DESCRIPTION("RTL9300 I2C controller driver");
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MODULE_LICENSE("GPL");
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