455 lines
12 KiB
C
455 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2025 Broadcom */
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#ifndef _BNGE_NETDEV_H_
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#define _BNGE_NETDEV_H_
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#include <linux/bnxt/hsi.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/refcount.h>
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#include "bnge_db.h"
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struct tx_bd {
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__le32 tx_bd_len_flags_type;
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#define TX_BD_TYPE (0x3f << 0)
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#define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
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#define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
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#define TX_BD_FLAGS_PACKET_END (1 << 6)
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#define TX_BD_FLAGS_NO_CMPL (1 << 7)
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#define TX_BD_FLAGS_BD_CNT (0x1f << 8)
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#define TX_BD_FLAGS_BD_CNT_SHIFT 8
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#define TX_BD_FLAGS_LHINT (3 << 13)
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#define TX_BD_FLAGS_LHINT_SHIFT 13
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#define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
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#define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
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#define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
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#define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
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#define TX_BD_FLAGS_COAL_NOW (1 << 15)
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#define TX_BD_LEN (0xffff << 16)
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#define TX_BD_LEN_SHIFT 16
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u32 tx_bd_opaque;
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__le64 tx_bd_haddr;
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} __packed;
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struct rx_bd {
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__le32 rx_bd_len_flags_type;
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#define RX_BD_TYPE (0x3f << 0)
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#define RX_BD_TYPE_RX_PACKET_BD 0x4
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#define RX_BD_TYPE_RX_BUFFER_BD 0x5
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#define RX_BD_TYPE_RX_AGG_BD 0x6
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#define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
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#define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
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#define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
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#define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
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#define RX_BD_FLAGS_SOP (1 << 6)
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#define RX_BD_FLAGS_EOP (1 << 7)
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#define RX_BD_FLAGS_BUFFERS (3 << 8)
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#define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
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#define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
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#define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
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#define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
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#define RX_BD_LEN (0xffff << 16)
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#define RX_BD_LEN_SHIFT 16
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u32 rx_bd_opaque;
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__le64 rx_bd_haddr;
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};
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struct tx_cmp {
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__le32 tx_cmp_flags_type;
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#define CMP_TYPE (0x3f << 0)
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#define CMP_TYPE_TX_L2_CMP 0
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#define CMP_TYPE_TX_L2_COAL_CMP 2
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#define CMP_TYPE_TX_L2_PKT_TS_CMP 4
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#define CMP_TYPE_RX_L2_CMP 17
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#define CMP_TYPE_RX_AGG_CMP 18
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#define CMP_TYPE_RX_L2_TPA_START_CMP 19
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#define CMP_TYPE_RX_L2_TPA_END_CMP 21
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#define CMP_TYPE_RX_TPA_AGG_CMP 22
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#define CMP_TYPE_RX_L2_V3_CMP 23
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#define CMP_TYPE_RX_L2_TPA_START_V3_CMP 25
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#define CMP_TYPE_STATUS_CMP 32
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#define CMP_TYPE_REMOTE_DRIVER_REQ 34
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#define CMP_TYPE_REMOTE_DRIVER_RESP 36
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#define CMP_TYPE_ERROR_STATUS 48
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#define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
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#define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
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#define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
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#define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
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#define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
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#define TX_CMP_FLAGS_ERROR (1 << 6)
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#define TX_CMP_FLAGS_PUSH (1 << 7)
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u32 tx_cmp_opaque;
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__le32 tx_cmp_errors_v;
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#define TX_CMP_V (1 << 0)
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#define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
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#define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
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#define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
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#define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
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#define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
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#define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
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#define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
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#define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
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#define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
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__le32 sq_cons_idx;
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#define TX_CMP_SQ_CONS_IDX_MASK 0x00ffffff
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};
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struct bnge_sw_tx_bd {
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struct sk_buff *skb;
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DEFINE_DMA_UNMAP_ADDR(mapping);
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DEFINE_DMA_UNMAP_LEN(len);
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struct page *page;
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u8 is_ts_pkt;
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u8 is_push;
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u8 action;
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unsigned short nr_frags;
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union {
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u16 rx_prod;
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u16 txts_prod;
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};
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};
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struct bnge_sw_rx_bd {
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void *data;
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u8 *data_ptr;
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dma_addr_t mapping;
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};
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struct bnge_sw_rx_agg_bd {
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netmem_ref netmem;
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unsigned int offset;
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dma_addr_t mapping;
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};
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#define HWRM_RING_ALLOC_TX 0x1
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#define HWRM_RING_ALLOC_RX 0x2
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#define HWRM_RING_ALLOC_AGG 0x4
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#define HWRM_RING_ALLOC_CMPL 0x8
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#define HWRM_RING_ALLOC_NQ 0x10
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struct bnge_ring_grp_info {
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u16 fw_stats_ctx;
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u16 fw_grp_id;
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u16 rx_fw_ring_id;
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u16 agg_fw_ring_id;
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u16 nq_fw_ring_id;
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};
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#define BNGE_RX_COPY_THRESH 256
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#define BNGE_HW_FEATURE_VLAN_ALL_RX \
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(NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
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#define BNGE_HW_FEATURE_VLAN_ALL_TX \
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(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
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enum {
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BNGE_NET_EN_GRO = BIT(0),
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BNGE_NET_EN_LRO = BIT(1),
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BNGE_NET_EN_JUMBO = BIT(2),
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};
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#define BNGE_NET_EN_TPA (BNGE_NET_EN_GRO | BNGE_NET_EN_LRO)
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/* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra
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* BD because the first TX BD is always a long BD.
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*/
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#define BNGE_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2)
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#define RX_RING(bn, x) (((x) & (bn)->rx_ring_mask) >> (BNGE_PAGE_SHIFT - 4))
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#define RX_AGG_RING(bn, x) (((x) & (bn)->rx_agg_ring_mask) >> \
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(BNGE_PAGE_SHIFT - 4))
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#define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
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#define TX_RING(bn, x) (((x) & (bn)->tx_ring_mask) >> (BNGE_PAGE_SHIFT - 4))
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#define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
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#define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNGE_PAGE_SHIFT - 4))
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#define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
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#define RING_RX(bn, idx) ((idx) & (bn)->rx_ring_mask)
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#define NEXT_RX(idx) ((idx) + 1)
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#define RING_RX_AGG(bn, idx) ((idx) & (bn)->rx_agg_ring_mask)
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#define NEXT_RX_AGG(idx) ((idx) + 1)
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#define BNGE_NQ_HDL_TYPE_SHIFT 24
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#define BNGE_NQ_HDL_TYPE_RX 0x00
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#define BNGE_NQ_HDL_TYPE_TX 0x01
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struct bnge_net {
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struct bnge_dev *bd;
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struct net_device *netdev;
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u32 priv_flags;
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u32 rx_ring_size;
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u32 rx_buf_size;
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u32 rx_buf_use_size; /* usable size */
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u32 rx_agg_ring_size;
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u32 rx_copy_thresh;
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u32 rx_ring_mask;
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u32 rx_agg_ring_mask;
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u16 rx_nr_pages;
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u16 rx_agg_nr_pages;
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u32 tx_ring_size;
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u32 tx_ring_mask;
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u16 tx_nr_pages;
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/* NQs and Completion rings */
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u32 cp_ring_size;
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u32 cp_ring_mask;
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u32 cp_bit;
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u16 cp_nr_pages;
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#define BNGE_L2_FLTR_HASH_SIZE 32
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#define BNGE_L2_FLTR_HASH_MASK (BNGE_L2_FLTR_HASH_SIZE - 1)
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struct hlist_head l2_fltr_hash_tbl[BNGE_L2_FLTR_HASH_SIZE];
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u32 hash_seed;
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u64 toeplitz_prefix;
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struct bnge_napi **bnapi;
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struct bnge_rx_ring_info *rx_ring;
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struct bnge_tx_ring_info *tx_ring;
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u16 *tx_ring_map;
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enum dma_data_direction rx_dir;
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/* grp_info indexed by napi/nq index */
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struct bnge_ring_grp_info *grp_info;
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struct bnge_vnic_info *vnic_info;
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int nr_vnics;
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int total_irqs;
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u32 tx_wake_thresh;
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u16 rx_offset;
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u16 rx_dma_offset;
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u8 rss_hash_key[HW_HASH_KEY_SIZE];
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u8 rss_hash_key_valid:1;
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u8 rss_hash_key_updated:1;
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int rsscos_nr_ctxs;
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u32 stats_coal_ticks;
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};
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#define BNGE_DEFAULT_RX_RING_SIZE 511
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#define BNGE_DEFAULT_TX_RING_SIZE 511
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int bnge_netdev_alloc(struct bnge_dev *bd, int max_irqs);
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void bnge_netdev_free(struct bnge_dev *bd);
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void bnge_set_ring_params(struct bnge_dev *bd);
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#if (BNGE_PAGE_SHIFT == 16)
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#define MAX_RX_PAGES_AGG_ENA 1
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#define MAX_RX_PAGES 4
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#define MAX_RX_AGG_PAGES 4
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#define MAX_TX_PAGES 1
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#define MAX_CP_PAGES 16
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#else
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#define MAX_RX_PAGES_AGG_ENA 8
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#define MAX_RX_PAGES 32
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#define MAX_RX_AGG_PAGES 32
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#define MAX_TX_PAGES 8
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#define MAX_CP_PAGES 128
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#endif
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#define BNGE_RX_PAGE_SIZE (1 << BNGE_RX_PAGE_SHIFT)
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#define RX_DESC_CNT (BNGE_PAGE_SIZE / sizeof(struct rx_bd))
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#define TX_DESC_CNT (BNGE_PAGE_SIZE / sizeof(struct tx_bd))
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#define CP_DESC_CNT (BNGE_PAGE_SIZE / sizeof(struct tx_cmp))
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#define SW_RXBD_RING_SIZE (sizeof(struct bnge_sw_rx_bd) * RX_DESC_CNT)
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#define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
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#define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnge_sw_rx_agg_bd) * RX_DESC_CNT)
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#define SW_TXBD_RING_SIZE (sizeof(struct bnge_sw_tx_bd) * TX_DESC_CNT)
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#define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
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#define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
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#define BNGE_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
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#define BNGE_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
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#define BNGE_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
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#define BNGE_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
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#define BNGE_MAX_TXR_PER_NAPI 8
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#define bnge_for_each_napi_tx(iter, bnapi, txr) \
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for (iter = 0, txr = (bnapi)->tx_ring[0]; txr; \
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txr = (iter < BNGE_MAX_TXR_PER_NAPI - 1) ? \
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(bnapi)->tx_ring[++iter] : NULL)
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#define BNGE_SET_NQ_HDL(cpr) \
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(((cpr)->cp_ring_type << BNGE_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx)
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struct bnge_stats_mem {
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u64 *sw_stats;
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u64 *hw_masks;
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void *hw_stats;
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dma_addr_t hw_stats_map;
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int len;
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};
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struct bnge_cp_ring_info {
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struct bnge_napi *bnapi;
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dma_addr_t *desc_mapping;
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struct tx_cmp **desc_ring;
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struct bnge_ring_struct ring_struct;
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u8 cp_ring_type;
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u8 cp_idx;
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u32 cp_raw_cons;
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struct bnge_db_info cp_db;
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};
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struct bnge_nq_ring_info {
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struct bnge_napi *bnapi;
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dma_addr_t *desc_mapping;
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struct nqe_cn **desc_ring;
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struct bnge_ring_struct ring_struct;
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u32 nq_raw_cons;
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struct bnge_db_info nq_db;
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struct bnge_stats_mem stats;
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u32 hw_stats_ctx_id;
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int cp_ring_count;
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struct bnge_cp_ring_info *cp_ring_arr;
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};
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struct bnge_rx_ring_info {
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struct bnge_napi *bnapi;
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struct bnge_cp_ring_info *rx_cpr;
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u16 rx_prod;
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u16 rx_agg_prod;
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u16 rx_sw_agg_prod;
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u16 rx_next_cons;
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struct bnge_db_info rx_db;
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struct bnge_db_info rx_agg_db;
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struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
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struct bnge_sw_rx_bd *rx_buf_ring;
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struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
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struct bnge_sw_rx_agg_bd *rx_agg_buf_ring;
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unsigned long *rx_agg_bmap;
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u16 rx_agg_bmap_size;
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dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
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dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
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struct bnge_ring_struct rx_ring_struct;
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struct bnge_ring_struct rx_agg_ring_struct;
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struct page_pool *page_pool;
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struct page_pool *head_pool;
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bool need_head_pool;
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};
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struct bnge_tx_ring_info {
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struct bnge_napi *bnapi;
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struct bnge_cp_ring_info *tx_cpr;
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u16 tx_prod;
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u16 tx_cons;
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u16 tx_hw_cons;
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u16 txq_index;
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u8 tx_napi_idx;
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u8 kick_pending;
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struct bnge_db_info tx_db;
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struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
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struct bnge_sw_tx_bd *tx_buf_ring;
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dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
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u32 dev_state;
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#define BNGE_DEV_STATE_CLOSING 0x1
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struct bnge_ring_struct tx_ring_struct;
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};
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struct bnge_napi {
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struct napi_struct napi;
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struct bnge_net *bn;
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int index;
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struct bnge_nq_ring_info nq_ring;
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struct bnge_rx_ring_info *rx_ring;
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struct bnge_tx_ring_info *tx_ring[BNGE_MAX_TXR_PER_NAPI];
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};
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#define INVALID_STATS_CTX_ID -1
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#define BNGE_VNIC_DEFAULT 0
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#define BNGE_MAX_UC_ADDRS 4
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struct bnge_vnic_info {
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u16 fw_vnic_id;
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#define BNGE_MAX_CTX_PER_VNIC 8
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u16 fw_rss_cos_lb_ctx[BNGE_MAX_CTX_PER_VNIC];
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u16 mru;
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/* index 0 always dev_addr */
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struct bnge_l2_filter *l2_filters[BNGE_MAX_UC_ADDRS];
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u16 uc_filter_count;
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u8 *uc_list;
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dma_addr_t rss_table_dma_addr;
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__le16 *rss_table;
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dma_addr_t rss_hash_key_dma_addr;
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u64 *rss_hash_key;
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int rss_table_size;
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#define BNGE_RSS_TABLE_ENTRIES 64
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#define BNGE_RSS_TABLE_SIZE (BNGE_RSS_TABLE_ENTRIES * 4)
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#define BNGE_RSS_TABLE_MAX_TBL 8
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#define BNGE_MAX_RSS_TABLE_SIZE \
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(BNGE_RSS_TABLE_SIZE * BNGE_RSS_TABLE_MAX_TBL)
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u32 rx_mask;
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u8 *mc_list;
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int mc_list_size;
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int mc_list_count;
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dma_addr_t mc_list_mapping;
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#define BNGE_MAX_MC_ADDRS 16
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u32 flags;
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#define BNGE_VNIC_RSS_FLAG 1
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#define BNGE_VNIC_MCAST_FLAG 4
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#define BNGE_VNIC_UCAST_FLAG 8
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u32 vnic_id;
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};
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struct bnge_filter_base {
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struct hlist_node hash;
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struct list_head list;
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__le64 filter_id;
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u8 type;
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#define BNGE_FLTR_TYPE_L2 2
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u8 flags;
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u16 rxq;
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u16 fw_vnic_id;
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u16 vf_idx;
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unsigned long state;
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#define BNGE_FLTR_VALID 0
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#define BNGE_FLTR_FW_DELETED 2
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struct rcu_head rcu;
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};
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struct bnge_l2_key {
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union {
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struct {
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u8 dst_mac_addr[ETH_ALEN];
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u16 vlan;
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};
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u32 filter_key;
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};
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};
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#define BNGE_L2_KEY_SIZE (sizeof(struct bnge_l2_key) / 4)
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struct bnge_l2_filter {
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/* base filter must be the first member */
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struct bnge_filter_base base;
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struct bnge_l2_key l2_key;
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refcount_t refcnt;
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};
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u16 bnge_cp_ring_for_rx(struct bnge_rx_ring_info *rxr);
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u16 bnge_cp_ring_for_tx(struct bnge_tx_ring_info *txr);
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void bnge_fill_hw_rss_tbl(struct bnge_net *bn, struct bnge_vnic_info *vnic);
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#endif /* _BNGE_NETDEV_H_ */
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