80 lines
3.4 KiB
C
80 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
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#ifndef _HINIC3_CSR_H_
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#define _HINIC3_CSR_H_
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#define HINIC3_CFG_REGS_FLAG 0x40000000
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#define HINIC3_REGS_FLAG_MASK 0x3FFFFFFF
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#define HINIC3_VF_CFG_REG_OFFSET 0x2000
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/* HW interface registers */
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#define HINIC3_CSR_FUNC_ATTR0_ADDR (HINIC3_CFG_REGS_FLAG + 0x0)
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#define HINIC3_CSR_FUNC_ATTR1_ADDR (HINIC3_CFG_REGS_FLAG + 0x4)
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#define HINIC3_CSR_FUNC_ATTR2_ADDR (HINIC3_CFG_REGS_FLAG + 0x8)
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#define HINIC3_CSR_FUNC_ATTR3_ADDR (HINIC3_CFG_REGS_FLAG + 0xC)
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#define HINIC3_CSR_FUNC_ATTR4_ADDR (HINIC3_CFG_REGS_FLAG + 0x10)
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#define HINIC3_CSR_FUNC_ATTR5_ADDR (HINIC3_CFG_REGS_FLAG + 0x14)
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#define HINIC3_CSR_FUNC_ATTR6_ADDR (HINIC3_CFG_REGS_FLAG + 0x18)
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#define HINIC3_FUNC_CSR_MAILBOX_DATA_OFF 0x80
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#define HINIC3_FUNC_CSR_MAILBOX_CONTROL_OFF (HINIC3_CFG_REGS_FLAG + 0x0100)
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#define HINIC3_FUNC_CSR_MAILBOX_INT_OFF (HINIC3_CFG_REGS_FLAG + 0x0104)
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#define HINIC3_FUNC_CSR_MAILBOX_RESULT_H_OFF (HINIC3_CFG_REGS_FLAG + 0x0108)
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#define HINIC3_FUNC_CSR_MAILBOX_RESULT_L_OFF (HINIC3_CFG_REGS_FLAG + 0x010C)
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#define HINIC3_CSR_DMA_ATTR_TBL_ADDR (HINIC3_CFG_REGS_FLAG + 0x380)
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#define HINIC3_CSR_DMA_ATTR_INDIR_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x390)
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/* MSI-X registers */
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#define HINIC3_CSR_FUNC_MSI_CLR_WR_ADDR (HINIC3_CFG_REGS_FLAG + 0x58)
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#define HINIC3_MSI_CLR_INDIR_RESEND_TIMER_CLR_MASK BIT(0)
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#define HINIC3_MSI_CLR_INDIR_INT_MSK_SET_MASK BIT(1)
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#define HINIC3_MSI_CLR_INDIR_INT_MSK_CLR_MASK BIT(2)
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#define HINIC3_MSI_CLR_INDIR_AUTO_MSK_SET_MASK BIT(3)
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#define HINIC3_MSI_CLR_INDIR_AUTO_MSK_CLR_MASK BIT(4)
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#define HINIC3_MSI_CLR_INDIR_SIMPLE_INDIR_IDX_MASK GENMASK(31, 22)
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#define HINIC3_MSI_CLR_INDIR_SET(val, member) \
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FIELD_PREP(HINIC3_MSI_CLR_INDIR_##member##_MASK, val)
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/* EQ registers */
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#define HINIC3_AEQ_INDIR_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x210)
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#define HINIC3_CEQ_INDIR_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x290)
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#define HINIC3_EQ_INDIR_IDX_ADDR(type) \
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((type == HINIC3_AEQ) ? HINIC3_AEQ_INDIR_IDX_ADDR : \
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HINIC3_CEQ_INDIR_IDX_ADDR)
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#define HINIC3_AEQ_MTT_OFF_BASE_ADDR (HINIC3_CFG_REGS_FLAG + 0x240)
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#define HINIC3_CEQ_MTT_OFF_BASE_ADDR (HINIC3_CFG_REGS_FLAG + 0x2C0)
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#define HINIC3_CSR_EQ_PAGE_OFF_STRIDE 8
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#define HINIC3_AEQ_HI_PHYS_ADDR_REG(pg_num) \
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(HINIC3_AEQ_MTT_OFF_BASE_ADDR + (pg_num) * \
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HINIC3_CSR_EQ_PAGE_OFF_STRIDE)
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#define HINIC3_AEQ_LO_PHYS_ADDR_REG(pg_num) \
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(HINIC3_AEQ_MTT_OFF_BASE_ADDR + (pg_num) * \
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HINIC3_CSR_EQ_PAGE_OFF_STRIDE + 4)
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#define HINIC3_CEQ_HI_PHYS_ADDR_REG(pg_num) \
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(HINIC3_CEQ_MTT_OFF_BASE_ADDR + (pg_num) * \
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HINIC3_CSR_EQ_PAGE_OFF_STRIDE)
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#define HINIC3_CEQ_LO_PHYS_ADDR_REG(pg_num) \
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(HINIC3_CEQ_MTT_OFF_BASE_ADDR + (pg_num) * \
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HINIC3_CSR_EQ_PAGE_OFF_STRIDE + 4)
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#define HINIC3_CSR_AEQ_CTRL_0_ADDR (HINIC3_CFG_REGS_FLAG + 0x200)
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#define HINIC3_CSR_AEQ_CTRL_1_ADDR (HINIC3_CFG_REGS_FLAG + 0x204)
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#define HINIC3_CSR_AEQ_PROD_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x20C)
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#define HINIC3_CSR_AEQ_CI_SIMPLE_INDIR_ADDR (HINIC3_CFG_REGS_FLAG + 0x50)
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#define HINIC3_CSR_CEQ_PROD_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x28c)
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#define HINIC3_CSR_CEQ_CI_SIMPLE_INDIR_ADDR (HINIC3_CFG_REGS_FLAG + 0x54)
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#endif
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