123 lines
3.2 KiB
C
123 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
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#ifndef _HINIC3_EQS_H_
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#define _HINIC3_EQS_H_
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#include <linux/interrupt.h>
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#include "hinic3_hw_cfg.h"
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#include "hinic3_queue_common.h"
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#define HINIC3_MAX_AEQS 4
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#define HINIC3_MAX_CEQS 32
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#define HINIC3_AEQ_MAX_PAGES 4
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#define HINIC3_CEQ_MAX_PAGES 8
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#define HINIC3_AEQE_SIZE 64
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#define HINIC3_CEQE_SIZE 4
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#define HINIC3_AEQE_DESC_SIZE 4
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#define HINIC3_AEQE_DATA_SIZE (HINIC3_AEQE_SIZE - HINIC3_AEQE_DESC_SIZE)
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#define HINIC3_DEFAULT_AEQ_LEN 0x10000
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#define HINIC3_DEFAULT_CEQ_LEN 0x10000
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#define HINIC3_EQ_IRQ_NAME_LEN 64
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#define HINIC3_EQ_USLEEP_LOW_BOUND 900
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#define HINIC3_EQ_USLEEP_HIGH_BOUND 1000
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enum hinic3_eq_type {
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HINIC3_AEQ = 0,
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HINIC3_CEQ = 1,
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};
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enum hinic3_eq_intr_mode {
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HINIC3_INTR_MODE_ARMED = 0,
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HINIC3_INTR_MODE_ALWAYS = 1,
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};
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enum hinic3_eq_ci_arm_state {
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HINIC3_EQ_NOT_ARMED = 0,
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HINIC3_EQ_ARMED = 1,
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};
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struct hinic3_eq {
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struct hinic3_hwdev *hwdev;
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struct hinic3_queue_pages qpages;
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u16 q_id;
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enum hinic3_eq_type type;
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u32 eq_len;
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u32 cons_idx;
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u8 wrapped;
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u32 irq_id;
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u16 msix_entry_idx;
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char irq_name[HINIC3_EQ_IRQ_NAME_LEN];
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struct work_struct aeq_work;
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};
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struct hinic3_aeq_elem {
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u8 aeqe_data[HINIC3_AEQE_DATA_SIZE];
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__be32 desc;
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};
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enum hinic3_aeq_type {
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HINIC3_HW_INTER_INT = 0,
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HINIC3_MBX_FROM_FUNC = 1,
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HINIC3_MSG_FROM_FW = 2,
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HINIC3_MAX_AEQ_EVENTS = 6,
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};
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typedef void (*hinic3_aeq_event_cb)(struct hinic3_hwdev *hwdev, u8 *data,
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u8 size);
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struct hinic3_aeqs {
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struct hinic3_hwdev *hwdev;
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hinic3_aeq_event_cb aeq_cb[HINIC3_MAX_AEQ_EVENTS];
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struct hinic3_eq aeq[HINIC3_MAX_AEQS];
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u16 num_aeqs;
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struct workqueue_struct *workq;
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/* lock for aeq event flag */
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spinlock_t aeq_lock;
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};
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enum hinic3_ceq_event {
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HINIC3_CMDQ = 3,
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HINIC3_MAX_CEQ_EVENTS = 6,
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};
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typedef void (*hinic3_ceq_event_cb)(struct hinic3_hwdev *hwdev,
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__le32 ceqe_data);
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struct hinic3_ceqs {
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struct hinic3_hwdev *hwdev;
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hinic3_ceq_event_cb ceq_cb[HINIC3_MAX_CEQ_EVENTS];
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struct hinic3_eq ceq[HINIC3_MAX_CEQS];
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u16 num_ceqs;
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/* lock for ceq event flag */
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spinlock_t ceq_lock;
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};
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int hinic3_aeqs_init(struct hinic3_hwdev *hwdev, u16 num_aeqs,
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struct msix_entry *msix_entries);
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void hinic3_aeqs_free(struct hinic3_hwdev *hwdev);
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int hinic3_aeq_register_cb(struct hinic3_hwdev *hwdev,
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enum hinic3_aeq_type event,
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hinic3_aeq_event_cb hwe_cb);
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void hinic3_aeq_unregister_cb(struct hinic3_hwdev *hwdev,
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enum hinic3_aeq_type event);
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int hinic3_ceqs_init(struct hinic3_hwdev *hwdev, u16 num_ceqs,
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struct msix_entry *msix_entries);
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void hinic3_ceqs_free(struct hinic3_hwdev *hwdev);
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int hinic3_ceq_register_cb(struct hinic3_hwdev *hwdev,
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enum hinic3_ceq_event event,
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hinic3_ceq_event_cb callback);
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void hinic3_ceq_unregister_cb(struct hinic3_hwdev *hwdev,
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enum hinic3_ceq_event event);
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#endif
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