142 lines
3.8 KiB
C
142 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
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#ifndef _HINIC3_MBOX_H_
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#define _HINIC3_MBOX_H_
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#include <linux/bitfield.h>
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#include <linux/mutex.h>
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struct hinic3_hwdev;
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struct mgmt_msg_params;
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#define MBOX_MSG_HEADER_SRC_GLB_FUNC_IDX_MASK GENMASK_ULL(12, 0)
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#define MBOX_MSG_HEADER_STATUS_MASK BIT_ULL(13)
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#define MBOX_MSG_HEADER_SOURCE_MASK BIT_ULL(15)
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#define MBOX_MSG_HEADER_AEQ_ID_MASK GENMASK_ULL(17, 16)
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#define MBOX_MSG_HEADER_MSG_ID_MASK GENMASK_ULL(21, 18)
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#define MBOX_MSG_HEADER_CMD_MASK GENMASK_ULL(31, 22)
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#define MBOX_MSG_HEADER_MSG_LEN_MASK GENMASK_ULL(42, 32)
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#define MBOX_MSG_HEADER_MODULE_MASK GENMASK_ULL(47, 43)
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#define MBOX_MSG_HEADER_SEG_LEN_MASK GENMASK_ULL(53, 48)
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#define MBOX_MSG_HEADER_NO_ACK_MASK BIT_ULL(54)
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#define MBOX_MSG_HEADER_DATA_TYPE_MASK BIT_ULL(55)
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#define MBOX_MSG_HEADER_SEQID_MASK GENMASK_ULL(61, 56)
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#define MBOX_MSG_HEADER_LAST_MASK BIT_ULL(62)
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#define MBOX_MSG_HEADER_DIRECTION_MASK BIT_ULL(63)
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#define MBOX_MSG_HEADER_SET(val, member) \
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FIELD_PREP(MBOX_MSG_HEADER_##member##_MASK, val)
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#define MBOX_MSG_HEADER_GET(val, member) \
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FIELD_GET(MBOX_MSG_HEADER_##member##_MASK, le64_to_cpu(val))
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/* identifies if a segment belongs to a message or to a response. A VF is only
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* expected to send messages and receive responses. PF driver could receive
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* messages and send responses.
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*/
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enum mbox_msg_direction_type {
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MBOX_MSG_SEND = 0,
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MBOX_MSG_RESP = 1,
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};
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/* Indicates if mbox message expects a response (ack) or not */
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enum mbox_msg_ack_type {
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MBOX_MSG_ACK = 0,
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MBOX_MSG_NO_ACK = 1,
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};
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enum mbox_msg_data_type {
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MBOX_MSG_DATA_INLINE = 0,
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MBOX_MSG_DATA_DMA = 1,
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};
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enum mbox_msg_src_type {
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MBOX_MSG_FROM_MBOX = 1,
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};
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enum mbox_msg_aeq_type {
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MBOX_MSG_AEQ_FOR_EVENT = 0,
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MBOX_MSG_AEQ_FOR_MBOX = 1,
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};
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#define HINIC3_MBOX_WQ_NAME "hinic3_mbox"
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struct mbox_msg_info {
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u8 msg_id;
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u8 status;
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};
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struct hinic3_msg_desc {
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u8 *msg;
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__le16 msg_len;
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u8 seq_id;
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u8 mod;
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__le16 cmd;
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struct mbox_msg_info msg_info;
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};
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struct hinic3_msg_channel {
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struct hinic3_msg_desc resp_msg;
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struct hinic3_msg_desc recv_msg;
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};
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struct hinic3_send_mbox {
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u8 __iomem *data;
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void *wb_vaddr;
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dma_addr_t wb_paddr;
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};
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enum mbox_event_state {
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MBOX_EVENT_START = 0,
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MBOX_EVENT_FAIL = 1,
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MBOX_EVENT_SUCCESS = 2,
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MBOX_EVENT_TIMEOUT = 3,
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MBOX_EVENT_END = 4,
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};
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struct mbox_dma_msg {
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__le32 xor;
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__le32 dma_addr_high;
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__le32 dma_addr_low;
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__le32 msg_len;
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__le64 rsvd;
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};
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struct mbox_dma_queue {
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void *dma_buf_vaddr;
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dma_addr_t dma_buf_paddr;
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u16 depth;
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u16 prod_idx;
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u16 cons_idx;
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};
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struct hinic3_mbox {
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struct hinic3_hwdev *hwdev;
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/* lock for send mbox message and ack message */
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struct mutex mbox_send_lock;
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struct hinic3_send_mbox send_mbox;
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struct mbox_dma_queue sync_msg_queue;
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struct mbox_dma_queue async_msg_queue;
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struct workqueue_struct *workq;
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/* driver and MGMT CPU */
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struct hinic3_msg_channel mgmt_msg;
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/* VF to PF */
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struct hinic3_msg_channel *func_msg;
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u8 send_msg_id;
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enum mbox_event_state event_flag;
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/* lock for mbox event flag */
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spinlock_t mbox_lock;
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};
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void hinic3_mbox_func_aeqe_handler(struct hinic3_hwdev *hwdev, u8 *header,
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u8 size);
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int hinic3_init_mbox(struct hinic3_hwdev *hwdev);
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void hinic3_free_mbox(struct hinic3_hwdev *hwdev);
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int hinic3_send_mbox_to_mgmt(struct hinic3_hwdev *hwdev, u8 mod, u16 cmd,
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const struct mgmt_msg_params *msg_params);
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int hinic3_send_mbox_to_mgmt_no_ack(struct hinic3_hwdev *hwdev, u8 mod, u16 cmd,
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const struct mgmt_msg_params *msg_params);
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#endif
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